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how implement sign-extention block

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mostafa272

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I want to impement the datapath and controller for I-type and R-type single cycle MIPS instructions with verilog,but I don't know for implementing sign-extention block and shift left block use which gates or functions,please guide me.
 

Sign extension is just repeating the highest order bit of the original value to all the 'to extend' bits on the left side of the new value.
 

sign extension is simply the repetition of sign bits for e.g...
a for bit number can be converted to 8-bits like this
1|111 ==> 1|1111111
0|111 ==> 0|0000111
 

thanks,but I want a function to do it.please write a function!
 

let you are converting a data bus 10bits wide to a data bus 15bits wide.
reg [9:0] bus_a; //bit10 is sign bit
reg [14:0] bus_b;

always @(*)
bus_b = {bus_a[9],bus_a[9],bus_a[9],bus_a[9],bus_a[9],bus_a[9], bus_a[8:0]};
 
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