Xilinx primitives libraries 11.2 version ISE

Hi friends,

I need Xilinx HDL Libraries Guide, version 11.2i if it exists , now i've just "Xilinx HDL Libraries Guide, version 9.1i" is there differencies between the two versions.

my second question, how can i use the xilinx primitives to code my own vhdl code.

regards:idea:

Maybe **broken link removed**?

thank you for your help,

but I cant understand how programing using xilinx primitives the problem is with INIT for example how can I know that the second 6-LUT of my design is X"ADC00" and not X"A555F"

regards

I am not 100% sure I understand the problem, but do you mean something like...



By the way, this is from page 172 of the Spartan-6 Libraries Guide for HDL Designs. This is for ISE 12.3 (because that's what I use), but you get the idea.

Hope that helps!

thank you,

sorry my english is not very well,

my question was How can I determine the exact value for INIT, I know that it depends on my design but which mamar can I attribute the exact value to INIT .

regards,

Ah okay, now I think I understand what you mean. I was working under assumption that you already had INIT values for your specific design. But you want to use a LUT6, and you want to use some other software to figure out the "INIT" value for you, based on some logic design you have in mind. Correct?

If yes, why would you want to? Usually the ISE tool will infer LUTs based on your verilog/vhdl design. Maybe you can provide some example of how you would want to use this?

Hi mrflibble,

an example is how to implement an counter.vhd using primitives. and my project is how interfacing ICAP with PowerPC440

regards,

ps: if you have some examples, send them to me.

hi lahrach,

Check out this comp.arch.fpga thread. There's a good explanation on how to do it for a LUT4.

hope that helps!

PS: I am still not sure why you would want to explicitly instantiate a LUT to make a counter, but I am sure you have your reasons. ;-)

thank you for ur help

good luck

--
Farid

You're welcome.

Also, check out this post: My FPGA Blog: Don't optimize my LUT please! It would be a bit sad to go to all the trouble of manually instantiating your LUT, only to have it "optimized" away for you. ;-)

Ah, I think he's doing it to remove some of the issues with partial-reconfiguration. I think the intent is to provide a standard programming stub. In such a case, every core would need to have the exact same implementation (or at least know the resources were not avaiable for general purpose use). This way, partially reconfigurable cores don't get half-configured before breaking the interface to ICAP.

In anycase, I'd suggest moving to 12.x if possible. the PR support has largely changed. If nothing else, the docs are a good read to see what the FPGA supports for efficient PR. most notable are frame-size and lack of re-INIT support for registers/rams (unless you reassert the GSR).

If you can't do this, I suggest taking HDL, and generate a netlist (ngc). From here, just use the ngc file and not the HDL. Then use fpga_editor to generate a UCF that provides the LOC/DIRT for all of the elements in your static design. This is probably better then trying to manually choose the LUT's, then manually LOC them, and then magically guess the DIRT strings. After all, if you don't LOC the LUT's, the tools will place them in different locations. If you don't provide DIRT's, the tools will decide how to route the signals.