Log!c
Newbie level 1
[note: I wrote the post topic wrong and now it isn't changing. I meant Cgd and cgdo!] Fixed - Keith
Hi everyone,
1) I'm still fairly new at simulating things in cadence. In my book the gate to drain capacitance is listed as Cgd. Is this the same as cgdo (gate drain overlap capacitance) in a spice model?
2) Also, as a side question, I was ran a DC-op analysis, and then went into some browser where you could look at a lot of different values for different transistors. You could right click on a property and view it in a "table". Some of the capacitance values (or so I thought) were negative. What's the deal with this 8-O
Hi everyone,
1) I'm still fairly new at simulating things in cadence. In my book the gate to drain capacitance is listed as Cgd. Is this the same as cgdo (gate drain overlap capacitance) in a spice model?
2) Also, as a side question, I was ran a DC-op analysis, and then went into some browser where you could look at a lot of different values for different transistors. You could right click on a property and view it in a "table". Some of the capacitance values (or so I thought) were negative. What's the deal with this 8-O
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