Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Signle clock CTS,which clock has priority?

Status
Not open for further replies.
C

cffyh

Newbie level 5
Joined
Sep 29, 2010
Messages
10
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,336
CTS for a signle clock,which clock has priority:Root clock or the generate(divided) clock?
 

U can declare a ignore_pin or stop_pin and do cts for Root clock, Then do for divided clock.

set_clock_tree_exceptions -stop_pins CELL/PIN
 
  • Like
Reactions: cffyh

    C

    cffyh

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top