Distortion and rubbish sensitivity

Hello,

I have recently designed a UHF receiver.
The MDS is probably -47dbm. I am hoping to achieve at least -108dbm.

Using a Marconi communication test set I injected directly 450.325MHz at -40dbm, 250Hz modulating frequency and 4.5KHz level.

The attached screen dumps shows a horribly disfigured 250Hz intelligence signal and the RF detector schematic. The intelligence signal was measured with an oscilloscope at "DATA". I12 and I13 are not fitted.

Does anyone have any ideas as to what potential causes of poor sensitivity and distortion I should investigate?

Lastly. The first amp in the RF section is designed for a small NF and a gain high enough to reduce the NF addition of the following stages. The problem is that the source impedance provided to the first amp needs to be a certain value for optimum NF. The source impedance is determined from the antenae and the matching network. This receiver will no doubt be worn on the b ody and so the antennae impedance will change when it comes into contact with nearby materials thereby destroying my noise figure. What do designers typically do to overcome this?

Thanks for your help

I don't know why you are using 3 inductors (I12, I13, I14) in parallel at the input of SA607. At this moment these inductors together with C37 and C38 resonates on 79MHz instead on 21.4MHz.

It does say in the text that L12 and L13 are not fitted.

I'd like to see all of the receiver. I can't see the RF front end in the attached doc.
However I have spotted a couple of potential problems.
The junction of Y6 and R59 should not connect direct to ground. Use a 100nF capacitor here to block the DC bias.

Also, you have a curious arrangement at the AF output. This is a non inverting op amp with 100k ohm in the feedback and you appear to be summing in a positive dc voltage to the inverted input.
Normally you would arrange a gain of two in this opamp but you have also a DC component. Is this some attempt at a squaring/levelling circuit for digital data?

Also, the PCB layout for the SA series of FM chips is extremely layout sensitive. You absolutely have to lay this chip out on a PCB with a continuous ground under it. This usually means a two layer PCB with the top layer as a big ground area. If you don't do this the chip will most likely go unstable and you will get a high residual RSSI voltage.

What RSSI voltage do you see with no RF input fed to the circuit? It should be low. If it is high your circuit could be unstable and will appear insensitive.

Also, what sensitivity do you see if you inject 21.4MHz direct at the IF node? i.e. bypass the RF front end.

My RSSI is less then 350mV. The schematic doesnt include the attenuator I had to add before Y4 to stabilise the circuit.

The DC block for Y6, R59 is a good pick. Cheers

At the AF output I was indeed trying to create a simple means of generating digital data.

I will try injecting 21.4 MHz. Good idea.

Thanks for your help guys.