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Why not? With refugee's circuit above, I can't see any "indirectness" nor any advantage for the PMOS compared to an NMOS (related to an unpredictable ESD event).... in terms of NMOS or PMOS as decoupling cap, i suggest you use PMOS, because the gate of PMOS is not directly connect to the power pad but to ground pad, though in ESD situation you have to consider all kind of ESD stress situation, for positive ESD stress at the power pad with respect to the ground pad, the gate oxide is not being stressed directly ...
as dick_freebird said, the best way to choose what type of MOS is acoording to the pulse ovestressed test data. but usually we dont have.Why not? With refugee's circuit above, I can't see any "indirectness" nor any advantage for the PMOS compared to an NMOS (related to an unpredictable ESD event).
I met with situation, when relatively big frame of decoupling capacitors (~20pF), placed near IO was failed during ESD stress.