ESD problem of mos cap between vin and ground.

During low voltage design, we would like to connect a cap between vin and ground to clean the power supply. And if we use a nmos as the cap, how could we protect its gate?

I have draw a pic to illustrate the question

vin pad is the power supply pad, right?
why you prefer to use NMOS as this decoupling cap?
usually this decoupling MOS cap has relatively large size, so that reactance is relatively small. what's more, you have dedicated ESD power clamps between power supply rail and ground, at ESD event, the power clamps should work effectively, so that the gate oxide of the NMOS cap wont be threatened.
anyway, PMOS is often used as decoupling cap other than NMOS.

Thanks for your reply, prcken.

The vin pad is the power supply pad.

I don't know what's the different between the nmos and pmos cap for this application.
In our design, we usually use the ggnmos structure as the ESD device. I'm a little worried about that the gate of nmos cap might be destroyed before the ESD protection device works.

if you use ggnmos as power pad ESD protection, there is a potential failure of the gate oxide especially in the CMOS process below 100nm.
for power pad ESD protection, power clamp is the mostly adopted scheme, power clamp is gate coupled ESD device with simple RC triggering circuit which can shunt ESD current by the channel of the main ESD MOSFET, while ggnmos is the mechanism of parasitic BJT.
in terms of NMOS or PMOS as decoupling cap, i suggest you use PMOS, because the gate of PMOS is not directly connect to the power pad but to ground pad, though in ESD situation you have to consider all kind of ESD stress situation, for positive ESD stress at the power pad with respect to the ground pad, the gate oxide is not being stressed directly, while for positive ESD stress at the ground pad with respect to the power pad, there is an intrinsic diode conduction between psub and power pad and clamps the voltage potential low so that the gate oxide reliability wont be an issue.

so, i suggest you use gate coupled NMOS as ESD power clamp and PMOS cap for decoupling, just put as many PMOS caps as you can, no need to worry.

prcken said:

... in terms of NMOS or PMOS as decoupling cap, i suggest you use PMOS, because the gate of PMOS is not directly connect to the power pad but to ground pad, though in ESD situation you have to consider all kind of ESD stress situation, for positive ESD stress at the power pad with respect to the ground pad, the gate oxide is not being stressed directly ...

Click to expand...

Why not? With refugee's circuit above, I can't see any "indirectness" nor any advantage for the PMOS compared to an NMOS (related to an unpredictable ESD event).

If you knew that a particular species of MOS was more
resilient to pulsed overstress, you'd prefer to use that.
But that kind of data is rarely sitting there waiting for
you.

The MOS cap is really no more "exposed" than any other
FET G-S, G-D - only less current-limited. If you punch it
out, you can bet other elements were not far behind.
You need a good ESD rail clamp and you need it distributed
to the same extent you distribute the capacitance or close
in to it.

You do need to be careful about antenna rules as the supply
bus is one of the largest antennae on any chip. And the
large MOS area will show up as supply leakage if you accrue
defects or damage.

Making the caps wider than long, in segments that favor
Rg and Rds (the latter probably the dominant de-Q-ing
term) will help their usefulness in quenching transient
supply current. When I build such MOS cap beds (and I
do it whenever possible, beats wasting area on density
fills) I overlay them with M-M plates criss-crossing the
poly for some added high-Q parallel capacitance.

You do not necessarily want your supply decoupling to
be extremely high Q, because that could make an
unfortunate resonance with bondwires.

erikl said:

Why not? With refugee's circuit above, I can't see any "indirectness" nor any advantage for the PMOS compared to an NMOS (related to an unpredictable ESD event).

Click to expand...

as dick_freebird said, the best way to choose what type of MOS is acoording to the pulse ovestressed test data. but usually we dont have.
one advantage of PMOS better than that of NMOS is PMOS nwell to substrate can contribute certain capacitance due to the parasitic capacitance besides its explicit gate oxide cap.

I met with situation, when relatively big frame of decoupling capacitors (~20pF), placed near IO was failed during ESD stress, because it was less resistive than power clamp in that case. So I recommend to have a few ohms connection of NMOS or PMOS capacitor's gate to power rail in any case,- to guarantee that most effective discharge pass is through power clamp.

This will not help you, because ballast resistors only help
when there is current flow, and if you have current flow
in the gate oxide you're already dead.

Unless you put a backstop clamp inboard of the resistor,
as you see in digital input pad cells. But the amount of
resistance you would need, to make that clamp much
more effective than the rail clamps already are, will make
the capacitor not very helpful.

mikersia said:

I met with situation, when relatively big frame of decoupling capacitors (~20pF), placed near IO was failed during ESD stress.

Click to expand...

for this specific case,i think you have to look at it failed at which ESD zapping combination, and at what ESD level it failed, failed during positive zap or negative zap, and so on
what do you mean placed near IO? but it is still connected between power pad and ground rail, right?
usually, you will meet the situation that the turn-on resistance of your power clamps is not that much small, the clamping voltage will be built up as ESD stress current increases, and finally exceeds the breakdown voltage of gate oxide of the decoupling MOS caps.

Pls, don't firget that local clamp, nearest to ESD event, is most effective due to bus resistance to main power clamps. During fast ESD transients charge is redistributed among all nets in according to it's AC (!) impedance, which for capacitors (gate also!) is inversly proportional to transition time. And therefore starting from some fast ESD transients a nearest to ESD zapped IO capacitors may serve as local clamp, if it's impedance will lower than designated power ESD clamp. It was exactly case which I met.