[SOLVED] I/O Pin protection for FPGA

Hi, I'm new in the forum, my english isn't so good but i hope that you understand.

Here's the problem:
I have a Digilent Nexys2 FPGA, and i'm in a project that is about a XY positioner, and for that project, i have to read from 4 sensors, 1x CNY70 (IR sensor), 2x Ultrasonic sensors and another one that we don't have yet.

Here's the specs for ultrasonic sensor:
"world wide web".robot-electronics.co.uk/htm/srf05tech.htm

So, ultrasonic sensor gives me a 5v signal that i have to read through the FPGA, and there's the problem, FPGA works with 3.3v, so...

Does anyone knows a circuit or something that let me work with my ultrasonic sensor with no problems?
A friend told me about "buffers" but i don't have much idea, any suggestions, any circuit that helps?

Thanks for reading.

use op amp as a buffer or use voltage converter IC.


More on buffer: www.eecs.tufts.edu/~dsculley/tutorial/opamps/opamps5.html

i did this circuit with AO, and i think it will do the job.
**broken link removed**

A friend also recomended an IC buffer like 74HC244 to avoid unwanted discharges to FPGA, what do you think about this?

Well you can make it with just one opamp. Just make a voltage divider with the output connected to the positive input of the opamp. Than connect the negative input with the output (voltage follower). As your opamp got rails bigger than you need i would sugest you using a zenner for further protection. You could also use many other solutions as dual supply voltage converter and quickswithes.

I just wanna say thanks, i used AmpOp's as a link between FPGA and Power Stage, and i used Buffers too, now my steppers motors are moving, and from here it's just programming in VHDL and Matlab, thank you very much.