65nm process study before doing real design

hi all
before doing real analog circuit design in 65nm CMOS process, i want to emulate the device charaterisitics and get to know all the effects that differ from 0.13µm or 0.18µm processes, and what kind of models (gate direct tunneling current model, monte carlo model, mismatch model, etc.) should be included in the spice simulation?
any comments are welcome.
thanks
Kehan

hi, kehan,
good question!

prcken said:

hi all
before doing real analog circuit design in 65nm CMOS process, i want to emulate the device charaterisitics and get to know all the effects that differ from 0.13µm or 0.18µm processes, and what kind of models (gate direct tunneling current model, monte carlo model, mismatch model, etc.) should be included in the spice simulation?
any comments are welcome.
thanks
Kehan

Click to expand...

I think noise also is worth to be studied.

I strongly advice you to use Silvaco tools.
they have the full design flow, from process characterization to device simulation, with enhanced atomic level analysis (carriers velocity & density, tunneling effects ...).
good luck.

I would much rather have a waffle-pack of PCM dice, and a
pad-out, than any amount of simulation. Especially as you are
quite unlikely to obtain the process flow or construction info
any such simulation would need, to be at all accurate.

It's more useful to check the real transistor behaviors against
the PDK models, than to try and "validate" those models from
yet another abstraction.

And in the end you will likely be using the standard models
and discovered "don't do that" / "don't believe that" guides
anyway.

Malek Lamari said:

I strongly advice you to use Silvaco tools.
they have the full design flow, from process characterization to device simulation, with enhanced atomic level analysis (carriers velocity & density, tunneling effects ...).
good luck.

Click to expand...

i think process flow is needed for using TCAD tools like Slivaco , but usually the process flow is confidential.

---------- Post added at 13:29 ---------- Previous post was at 13:21 ----------

****_freebird said:

I would much rather have a waffle-pack of PCM dice

Click to expand...

what does PCM stand for?
good idea, but right now i have no chance to do real silicon measurement in 65nm process

prcken said:

what does PCM stand for?

Click to expand...

Process Control Monitor, an extra die inserted a few times on the wafer (or in the saw lane), containing several standard devices, enabling the measurement of process variations over the wafer and over the lot(s).