Clock signal not applied at a CLK pin of squential element

If I applied a clock signal to some combinatorial logic elements, because at those places it is not directly applied to CLK pin of sequential elements it is treated as asynchronous by RTL Compiler and SoC Encounter?

The timing paths, from this clock to the chip output (synchronous with the same clock) or to the D-pin of a sequential element, are not analyzed. How do I force RTL Compiler and SoC Encounter to include these paths in the timing analysis? Thank you.

Re: Clock signal not applied at a CLK pin of squential eleme

I don't completely follow. Yes, clock signals generally connect to clock pins on sequential cells (flops, latches, RAMs) but they can also be applied to combinatorial logic (like clock gates) or data input to flops (such as to make a divider.) If your clock signal is going to combinatorial logic you have to carefully make special timing constraints to make sure the synthesis and P&R tools understand your intention.

If you can give some more details I maybe able to help more.

Re: Clock signal not applied at a CLK pin of squential eleme

I think that i understand what you asked.Here is my take:
Any input on macro cell can be a clock .But the problem is that you will have races .The circuit will be asynchronous and hard to determine the behavior.Though for you "it should work ".The synthesis tool can not garantee that the timings are respected .Every time you will route the chip different timings will be obtained That's is the reason that you have specific lines for the clock .You should use those lines .And use other signal qualifiers in the macrocell .Asynchronous designs are a bad aidea.
I think that to try to declare those constrains to a tool will make very hard to follow .I recall 15 years ago when i was started .I tried to do something similar.The router will work the WHOLE day !.The results were not very good .

Re: Clock signal not applied at a CLK pin of squential eleme

eltonjohn's post helped me understand your situation more, I think.

If you want to constraint an asynchronous path you can use set_max_delay and set_min_delay. You still have to be very careful to avoid race conditions, unstable loops, metastability, etc. but it is possible.

Re: Clock signal not applied at a CLK pin of squential eleme

Do you generate the clock tree with these logic? You can move the root of clock to after these logic.
Or you need update with synchronization design for these logic.