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DC Synthesis Interview Questions - Help Required

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srinivasansreedharan

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Hi,
Can anyone explain answers for the following questions?
1. What is the difference between Total Negative Slack and Worst Negative Slack?
2. Does Synopsis DC do the static timing analysis based on the input slope and output cap info of cells present in the critical path of a design. If so, how does it calculate the timing of a circuit based on the input slope and output cap info of the cells?
 

srinivasansreedharan said:
Hi,
Can anyone explain answers for the following questions?
1. What is the difference between Total Negative Slack and Worst Negative Slack?
2. Does Synopsis DC do the static timing analysis based on the input slope and output cap info of cells present in the critical path of a design. If so, how does it calculate the timing of a circuit based on the input slope and output cap info of the cells?
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1. Total Neg Slack (TNS) is the sum of the slack of all violating paths or endpoints. Worst Neg Slack (WNS) is the slack of the violating path with the largest magnitude (most negative).

2. 2-D Look-up tables, usually. One axis is input slew, one axis is load, the delay is the number in the table in the .lib/.db at that intersection.

edit: if you're interviewing for a position that asked you these questions and you don't know them, you probably won't last long at the job even if you get it, unless you start studying a lot. Good luck.
 
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    ivlsi

    ivlsi

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Thanks for the reply. Also can you tell me the significance of -ignore_tns commands during area optimization during synthesis
 

-ignore_tns means area should be given priority over Total Negative Slack (and thus timing in general.) I've never really used it except during initial synthesis to get a rough area estimate even when netlist/constraints aren't mature. This is important so you can start estimating die size / package during early design stages, but not usually used for real synthesis for signoff to backend..
 

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