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synthesis division operator /

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mo.khairy.mo

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Hi all
can i use division operator in vhdl and can it synthesized using XST?

what i need to do is to divide two registers each 32b
can any one help me to do this using VHDL?!

thanks in advance
 

Hi,

When you mean a real division and not a shift operation (divide by power of 2) I would have a look at there divider available in Core Generator.

Devas
 
With Altera Q.uartus and Cyclone III FPGA, implementing a 32bit/32bit=32bit unsigned divider required the below amount of logic elements with different methods:

2946 LEs using the divide function suggested by vipinlal
1112 LEs inferring a divider MegaFunction by simply writing result <= a/b;
203 LEs using a serial divider component (takes about 32 clock cycles)
 

Thank all,
@ devas i do what u advice me here is my code
Code: 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;


ENTITY div IS
-- Declarations
	port(
		clk 	: in  std_logic;
		rst 	: in  std_logic;
		A		: in  unsigned(3 downto 0);
		B		: in  unsigned(3 downto 0);
		C		: out unsigned(3 downto 0)
		);
END div ;

-- hds interface_end
ARCHITECTURE rtl OF div IS
BEGIN
	process(clk,rst)
	begin
		if rst = '1' then
 	    	C <= (others=>'0');
		elsif (rising_edge(clk))then
			C <= A / B;
		end if;
	end process;
END rtl;

in the behavioral simulation it works well but when i synthesize it using XST i've the following error

Code: 
line 25: Can not simplify operator DIV.
 

Hi,

It seems XST does not allow to use the / operator when this division does not result in a simple shift operation (divide by power of 2). As suggested before have a look at there Core Generator Divider core. I suppose this core can divide without the restriction to be a power of 2.

Devas
 

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