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HELP: Can i hook non input/output signal to testbench?

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akira12345

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Hi,

I am using modelsim. I would like to hook up non input/out signal to testbench from design unit.
Example

Design unit:
module design_unit( out1, out2, in1, in2);
input in1, in2;
output reg out1, out2;
.......
reg [5:0] int_reg;
......
endmodule


Testbench unit:
module design_unit_tb();
reg in1, in2;
wire out1, out2;

........

//my problem is how do i make it as below
always @(int_reg) <--- int_reg is not input/output of design unit
.........
endmodule

I would like to capture the int_reg signal and print to text file, but i dont know how to hook out int_reg (reg type) to testbench.

Thanks for your help. :D
 

You can just use the hierarchical path to any signals to reference it. Assuming the module design_unit is the top-level module (i.e. not instantiated anywhere), then you can do this:

always @(design_unit.int_reg) <--- int_reg is not input/output of design unit


If the module design_unit is instantiated in design_unit_tb as design_unit_inst, for example, then you can do this:

always @(design_unit_tb.design_unit_inst.int_reg) <--- int_reg is not input/output of design unit

- Hung
 

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    akira12345

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