JFET equations considering temperature value

Hello,

I use a jFET to obtain a quadratic transfer characteristic, and from simulation I observed that Vp does vary a bit with temperature (a few mV).
I would like to know a JFET equation that takes into account temperature value, to do a correction in software... but so far I only found the classical equation:
ID=IDSS(1-VGS/Vp)^2


Thanks

try to get a copy of practical electronics calculations and formulae
by F.A.Wilson it's an old book but it's helped me a few times

steve

but so far I only found the classical equation

Click to expand...

You'll find a lot more in a serious literature search. You can also refer to SPICE FET models, that also include temperature
dependencies, but they aren't suitable for a basic compensation of temperature effects.

If you refer to the simple quadratic characteristic as quoted above, two reservations apply:
- It's only valid for a central range of the characteristic. Low current (subtreshold range) as well as high current range
(series resistances get important) are not reproduced correctly
- both parameter (IDSS and Vp) are temperature dependant

For square or square root functional circuits, you can easily cancel Vp temperature effects by using a FET pair. So the IDSS temperature dependency
is the more important problem.

I reviewed my 1984 diploma thesis (about wideband square root circuits) and found this representation of FET temperature dependant behaviour:


I also found empirical measurements of deviation from quadratic behaviour, that can bring FET function generator circuits down to earth...

Thanks for your answer.
I'm trying to use the JFET in a half cycle AC milli/micro wattmeter, but unfortunately the characteristic is not precisely quadratic.
I used an BF245B transistor, the SPICE simulation shows a quadratic graph, but the prototype has big measurement errors. The transistor is biased at VGS≈VT, ID≈1nA, applying the voltage in the source, the gate is connected to the hot terminal of the load resistor, and I measure the averaged drain current.
I think I will try other types of JFET to get a more precise characteristic. It's strange that the SPICE simulation showed perfect quadratic behaviour.

It's strange that the SPICE simulation showed perfect quadratic behaviour.

Click to expand...

I think it's not strange, it's a consequence of the simplified JFET SPICE models. They lag behind at "level 1" of the MOSFET
models. Furthermore, additional parameters, that are available to describe e.g. the temperature dependency are not set in the
BF245 model parameters, as you can easily check.

I also noticed, that HSPICE implements level 2 and 3 JFET models, the latter e.g. include additional parameters for the subthreshold
region, which should better reproduce the behaviour at 1 nA Id.

See www.ece.rochester.edu/courses/ECE222/hspice/hspice_devmod.pdf

The transistor is actually biased at ID=10...100nA. A current log amp follows and then the uC part to diplay the value measured on a LED display.
Initially I was counting on the half cycle quadratic characteristic, but now I think I will use a look-up table in the uC, not being "true RMS" anymore Anyway it should be better than an ordinary diode detector, and have a more stable input impedance.