AdvaRes
Advanced Member level 4
Hi guys,
When the PLL locks I zoom in the signal that controls the VCO. The signals has periodic ripples that occurs at the speed of the PFD/CP. The controle Voltage range is between 0 and VDD. The ripple represent 3.6% of VDD.
Is that big or normal ? Are these ripples the responsible of the reference spurs in PSD plot of the PLLs output signal ?
How to eliminate them without changing the BW and phase margine of the PLL ?
Thanks in advance for your participation.
When the PLL locks I zoom in the signal that controls the VCO. The signals has periodic ripples that occurs at the speed of the PFD/CP. The controle Voltage range is between 0 and VDD. The ripple represent 3.6% of VDD.
Is that big or normal ? Are these ripples the responsible of the reference spurs in PSD plot of the PLLs output signal ?
How to eliminate them without changing the BW and phase margine of the PLL ?
Thanks in advance for your participation.