verilog coding for muller c-element

vlsi

i want verilog coding for muller c-element

Re: vlsi

Hi ,

i guess you must be a newbie to this VLSI forum


I gone through wikipedia
https://en.wikipedia.org/wiki/C-element

this is a simple circuit which can be done in verilog. they have given the truth tabe also....

Go through the design and try it yourself and let me know if u have any difficulties

Added after 28 minutes:

muller C gate is a gate used for synchronisation

the truth table is like if all the inputs are 1 the output is 1 and if all the inputs r 0 the output is 0....

https://tams-www.informatik.uni-ham...emos/16-flipflops/70-cgate/muller-cgate3.html


module Muller_C_Gate(in_a,in_b,in_c,out);
input in_a;
input in_b;
input in_c;

output out;

assign out = ({in_a,in_b,in_c} == 3'b111)?1{in_a,in_b,in_c} == 3'b000)?0ut;

endmodule


this is not an optimized code. but you can try it with structural design.

check the link above and try it in structural design.. what i have written is a behavioral code

all the best

the assign statement is giving error. Is there a way to eliminate the error? it says we cannot use the left hand side OUT in the right hand side of the statement.