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Basic problem on set_max_delay in DC

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linny_chen

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Dear friends,

I have a VHDL design. I would like to set a time constraint from an output port "out" of entity "a" to an input port "in" of entity "b" using the command set_max_delay. What should appear after the "-from" and "-to" options of the command? Thanks a lot!

KR,

Added after 5 minutes:

By the way, there is no register between the two ports. And probably there is only a wire between the ports. Could anyone tell me how I should write this command? I tried a lot of options, even like set_max_delay 0.1 -from [get_ports {a/out}] -to [get_ports {b/in}] which does not work.
 

Hi linny_chen,

Why do you need that? Are your modules a/b black boxes?
If no DC will do it and you don't need to set constrains there.

Best Regard,
Tiksan
 

Hi,

thank you for you reply. Actually, I have another path between the two ports, which is registered. I would like to set constraint on the two modules separately, and then set a maximum delay on the bypassing wire between the two ports. After synthesis of both modules, I can know whether this bypassing wire can be used or not under some global timing constraint.
 

Hi linny_chen,

Try the following commands:

set pin_a [get_pins [find pin <instance name>/<pin name>]]
set pin_b [get_pins [find pin <instance name>/<pin name>]]
set_max_delay <delay_value> -from $pin_a -to $pin_b

You should use instance name not design name.

Use "find pin" command to see all pins in the design.

Let me know about your progress.

Best Regards,
Syswip
http://syswip.com
 
Hi, Syswip,

Thanks for your reply!

You can consider module a/b as black boxes. It works for our case to set specific constraints for module a/b and path between them. One other question is, when we set specific time constraints like this, the design compiler would not consider them when calculating the critical path. How could we make design compiler also considering this individual constraints?

Kind regards,

linny_chen
 

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