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associative array in systemverilog

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sree205

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Hi all,
Is there a way to implement associative array in system verilog inside an always block or in a class ? in the tutorials and in books, i see that its declared mostly in initial blocks.

My application needs knowledge of previous data stored. Gist of what i'm looking for is like this,

if(write)
assciative_arr[addr] = input_data;
else if (read)
output_data = associative_arr[addr]

any alternative suggestions to implement this are also welcome.
 

Hi sree205,

Of course you can declare associative array inside a class.
I recommend you to check if exists or no current address before reading.
If your read address doesn't exist some tools can generate warnings.

Do it like this:
Code:
if(write) 
assciative_arr[addr] = input_data; 
else if (read) begin
  if(associative_arr.exists(addr))
    output_data = associative_arr[addr];
  else
     output_data = (0 or x...)
end

Bests,
Tiksan,
http://syswip.com/
 
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    sree205

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    pnirav

    Points: 2
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I found this explanation in one of the websites.

Create a class to represent a memory location (i.e. it has address and data properties). Create an associative array of this memory location class indexed by the address property.

Does this mean creating an array of objects? Is this in anyway better than just creating an associative array?
 

Creating an object of memory element and pushing it in a array has its own advantages if
a. you plan to implement a list of accesses to the same address.
(where in each address will store the history of accesses also)
i.e. scoreboarding in built in the memory.
b. If memory also needs to have snoop/nosnoop, relaxed ordering kind of protocol specific features.

If all that you want is a plain memory storage, then there is no use filling it as a object. Infact it goes onto increase the overhead on the storage.

Cheers,
eChipDesign.

=====================================================
eChip Design Labs
VLSI Training for Verilog and System Verilog
Nagercoil, TamilNadu

**broken link removed**

=====================================================
 

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