sree205
Advanced Member level 1
Hi all,
Is there a way to implement associative array in system verilog inside an always block or in a class ? in the tutorials and in books, i see that its declared mostly in initial blocks.
My application needs knowledge of previous data stored. Gist of what i'm looking for is like this,
if(write)
assciative_arr[addr] = input_data;
else if (read)
output_data = associative_arr[addr]
any alternative suggestions to implement this are also welcome.
Is there a way to implement associative array in system verilog inside an always block or in a class ? in the tutorials and in books, i see that its declared mostly in initial blocks.
My application needs knowledge of previous data stored. Gist of what i'm looking for is like this,
if(write)
assciative_arr[addr] = input_data;
else if (read)
output_data = associative_arr[addr]
any alternative suggestions to implement this are also welcome.