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how to simulate my coregen in modelsim?

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reg xilinx coregen

Dear experts

I have a doubt in coregen, how to simulate my coregen in modelsim.
How to map the library of xilinx with modelsim?

Thanks in advance..
 

Re: reg xilinx coregen

The Coregen Outputs a top module verilog file for u r core. U can take that and simulate. Inside the top module they will have lot of instantiations which also should be included in the project directory. You can get those libraries in the Xilinx Folder.
 

Re: reg xilinx coregen

Hi,

When you use Modelsim-XE, you should have the Xilinx libraries already, or you can download them from the Xilinx web-site.

When you use Modelsim, you can run the compxlib utility to compile the Xilinx libraries. You can find the compxlib utility in the <Xilinx install dir>/bin/nt

Devas
 
Re: reg xilinx coregen

thanks a lot guys..
I executed compxlib utility.. Its installed.
How to map those library to my modelsim..
am getting error " Instantiation of 'fifo' failed. The design unit was not found."
 

reg xilinx coregen

you use the file of .v generated by coregen as the file yours, of course you should add the liberary file of xilinx in you design.the path of liberar file is the paths of your ISE installed.
 

Re: reg xilinx coregen

Hi guys

Thanks for your answers..
Finally i got a solution.. my core is simulating in modelsim.
I did the following steps

1. In ISE, select the device in the sources window
2. find the the "Compile HDL Simulation libraries", right click and
select "Properties"
3. Set your preferences in dialog and apply and run the process.
4. In the preference u select a path, after run u will be getting library's like
simprim, simprims_ver, unisim, unisim_ver, xilinxcoreLib, xilinxcorelib_ver.
5. In this copy the files that u have in xilinxcorelib_ver and paste in ur modelsim work folder.

ur core will simualte..
 
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