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Synthesized my design, but where is output netlist (DC)?

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user_asic

user_asic

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The answer to this is probably very obvious, but I cant find my output netlist after I synthesize my code using DC. Doest the output netlist get dumped in the same directory as the original source file used in the design?

Thank you.
 

Hi,

DC won't dump the netlist automatically. You need to use write_netlist command to generate gate level netlist. Check your script.

Regards
 

    user_asic

    user_asic

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