verilog rokie, any help appreciated

Hi all,

I'm a novice Verliog programmer. just started out with Palnitkar's Verilog HDL n I'm stuck up with this very basic program in the exercise of the book.

Q: What would be the output of the following?
latch=4'd12;
$display ("The current value of latch= %b\n", latch);

Since this chunk does not compile as such, I tried to pad it up myself so that it compiles. Here it goes:
-----------------------------------------------------
module latch;
reg latch1;

initial
latch1 = 4'd12;

initial
$display ("The current value of latch1 = %b\n", latch1);
endmodule
-------------------------------------------------------

It did compile but I ran into an issue:
1. I expect the result--The current value of latch1 = 1100
But what i get is--The current value of latch1 = 0
Q: Why is it so?
I'm not familiar with the initial/begin/end statements as i'jus ventured into verilog n i tried to put it together by seein other examples which worked fine. But nevertheless do enlighten me with ur answers.

all wizards out there sorry if this Q has bugged u but there r more such comin in the future []

try

reg [3:0] latch1;

currently your latch1 is 1 bit wide...

you had declared the latch as 1 bit so u are getting only 1 bit.. try as mytechface has said.. u shld be able 2 get proper result....

haneet

Thanks a lot mytechface and haneet. Will try what u have suggested. So by default a reg variable is 1 bit wide, am I right?

Thanks a lot guys its workin!

yes.. u r right... by defauls a reg or wire are 1 bit unless u mention the bit width as stated earlier...

haneet