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CTS : Balancing to clock feeding to a MUX

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jyothia

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Hi,

Suppose from PLL o/p we have many clock comming out and each clock is going to a 2x1 MUX along with a TEST clock.
My question is how we go about balancing in this clock....
 

Hi
I think you should keep in mind that if there are some clocks should be balanced with each other. If so, you should put these clocks into one group to balance them.
Then you can clarify the sinks of the specified clock. Clock tree insertion tools will help you synthesize the clock tree well.
In you case, I think you can place the MUX near the PLL, then build the clock tree
from the output of the MUX.
You can upload a picture about the clock structure of your case. Then we will get
a thorough understanding.
Thanks
 
Hi,

Please find attached the scenario.
 

Hi.

I think you should talk with the logic designer first, to find out if the CLK1/CLK2/CLK3 will talk with each other. If so, you should make a group
to balance these clocks.
If they are separate clock domain, you can place these MUX near PLL first,
then using the clock insertion tool to build the clock tree from the output of the MUX
 

Hi, That is true that we need to balance CLK1,CLK2,CLK3...But do we need to balance test-clk also along with the other clk (clk1,clk2..)

If we need to balance then how can we go about it...
 

Hi

If you balance the functional clocks: clk1/clk2/clk3, then the test clock will also be balanced. Because they share the same buffer tree.
In my opinion, test clock in one domain should be balanced too, if you can.
but the skew requirement is not very critical as the functional clock.
So, if you put these MUX near the near the PLL, and group the output of the MUX
to build balanced clock tree. Then the test clock tree will be balaced too.
good luck!
Thanks!
 

Hello Friend,

We have implemented this kind of CT during our work.

1. Build seperate clock trees from each mux output. and balance the clock trees. One input is your test clock and the other is ur functional clock.

2. Take care of the latancies from the clock source to the mux inputs. I mean latency should be same.

Actually this methos would give a low timing aswell s area overheads. And we achieved the same.

I invite comments on this.

Regards,
SunilB
asic-dft.com
 

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