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How to choose Critical Path

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kurukuru

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Hi,

I'm a newbie seft-study FPGA and I don't quite understand about critical path. I don't quite understand what does it mean and don't know how to pick one critical path above the others. Would any one please tell me how or give me some hint or link that I can find my answer?

Thank you.

(not yet) kurukuru
 

Critical path is the path which has the most delay associated with it. When you synthesize a design to FPGA/ASIC and constrain it.. none of the paths will have zero delay.. there will be some amount of delay in terms of ns or ps associated with this.

The path with the longest delay is called the Critical Path. Critical path determines the Max frequency of operation of the ckt. Suppose the design has paths with delays of 2ns, 4ns and 8ns, the Critical path will be the path with 8ns delay and the max operating freq will be 1/8ns = 125MHz.
 

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    kurukuru

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Hi

vlsi_whiz, Thank you very much for your reply.

According to your reply Can I assume that program will automatically choose the mentioned critical path for me?

Thank you.
 

Yes, Synthesis tools will show you the critical path after it performs timing analysis. You can then further constrain the design to reduce the delays and improve the operating frequency.
 

Hi,

vlsi_whiz, Thank you very much for your kindly reply.
 

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