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[URGENT 20 pts] LVS problem

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AdvaRes

AdvaRes

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Hi members,
I have the following LVS problem. When I launch dracula I get the following error message:


ERROR: SCONNECT conflicts detected. ABORT ON SOFTCHK is specified - aborting.
*** Calibre finished with Exit Code: 4 ***

How to solve it ?

Thanks.
 

hi advares- you have to check that all substrate contacts are connected to ground and ntap contacts connected to supply.

cheers
 

    AdvaRes

    AdvaRes

    Points: 2
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Hi fixrouter4400,

I'm doing the layout of a second order filter. The filter is composed of 2 capacitance and 1 resistor. Each component have 3 pins: plus,minus and a third one named b.
I use this filter in my PLL.
In my design I dont need to connect the b pin to ground. When I do lvs check I got that error message.
Please tell me how to resolve this problem.
 

The B terminals in the scematic refer to the 'bulk' or 'body' connection of these devices, ie the substrate underneath them. Although capacitors and (poly) resistors do not connect to diffusion you should still connect these terminals in the schematic to whatever potential the substrate below them is tied to, vdd if over nwell and gnd if not. Often designers will specify that capacitors should be built over a (empty) nwell to give them some isolation from noise in the substrate.
 

    AdvaRes

    AdvaRes

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Pat_Mustard said:
The B terminals in the scematic refer to the 'bulk' or 'body' connection of these devices, ie the substrate underneath them. Although capacitors and (poly) resistors do not connect to diffusion you should still connect these terminals in the schematic to whatever potential the substrate below them is tied to, vdd if over nwell and gnd if not. Often designers will specify that capacitors should be built over a (empty) nwell to give them some isolation from noise in the substrate.
Click to expand...

Hi Pat_Mustard,
Yes this true. Actually I did connect the b terminals in the schematic to vdd/gnd but not in layout. The lvs become successfull but we get a new problem. When I try to do the pls simulation, the circuit behave like to be really be connected to Vdd/gnd.
 

You should not need to make any physical connections in layout for the backgate of resistors or capacitors other than your usual nWell / substrate connections. I dont really understand your problem with your extracted simulation, can you ellaborate?

Added after 26 minutes:

By usual nWell / substrate connections I mean making sure you have a strong connection from VDD to your nwell through diffusuion and likewise for GND to substrate (p-type).
 

    AdvaRes

    AdvaRes

    Points: 2
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Pat_Mustard said:
You should not need to make any physical connections in layout for the backgate of resistors or capacitors other than your usual nWell / substrate connections. I dont really understand your problem with your extracted simulation, can you ellaborate?

Added after 26 minutes:

By usual nWell / substrate connections I mean making sure you have a strong connection from VDD to your nwell through diffusuion and likewise for GND to substrate (p-type).
Click to expand...


Thanks Pat_Mustard,
I sent to you in PM some details. Did you saw them ?
 

Hi AdvaRes

The capacitor and the resistor bulk connection should under the local NWELL if it is connected to Supply (vc.

As far as i understand in your schematic that the capacitor and the resistor bulk connection is connected to supply(vc).

fill me in some information to help you more.

cheers
 

    AdvaRes

    AdvaRes

    Points: 2
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Hi advares,

pls see attached hope that helps you.
 

    AdvaRes

    AdvaRes

    Points: 2
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Hi fixrouter4400,
This helped a lot.
I gave you 10 pts for your help.
Thanks you.
 

Hi advares - do let me know if you still need help and clarification.

cheers
 

    AdvaRes

    AdvaRes

    Points: 2
    Helpful Answer Positive Rating
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