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BSD and SCAN insert question

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HolySaint

HolySaint

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jtag specification extest_train

I added pad cell in the rtl top module,
how can I insert bsd in my design?
I have two method(I use snps DC),
===============
top.v > top_bsd.v
top_bsd.v + other module > netlist.v
netlist.v > netlist_dft_ins.v
netlist_dft_ins.v > atpg
===============
top.v + other module > netlist.v
netlist.v > netlist_bsd_ins.v > netlist_dft_ins.v
netlist_dft_ins.v > atpg
===============

which one is the right flow?
the second one, when I check_bsd the tools coundn't find my pad cells,and sime of the pad cells' input and output had changed to connect wires that gened by the tools.

Who can give me an advice?
Thank you!!
 

bsd tap controller

who can hlp me?

nice to share ur idea~~
 

bsr cells for output pad

i do the second one
but when i sim the net it took errors

just like this:
At time 3454695000 : Incorrect output response (xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, expected x0xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
At label" 34544 AC Input Train Vectors EXTEST_TRAIN Shift-IR"


but when i sim the rtl_bsd.v there is no error.
 

bsd trst 1149.1

I think these two flows are equivelant.

And for the error, it's hard to tell without a real example.

DC is stupid. It often substitute pad cells for standcell if you haven't set don't touch on those pads. Hope it's just this issue.

HolySaint said:
I added pad cell in the rtl top module,
how can I insert bsd in my design?
I have two method(I use snps DC),
===============
top.v > top_bsd.v
top_bsd.v + other module > netlist.v
netlist.v > netlist_dft_ins.v
netlist_dft_ins.v > atpg
===============
top.v + other module > netlist.v
netlist.v > netlist_bsd_ins.v > netlist_dft_ins.v
netlist_dft_ins.v > atpg
===============

which one is the right flow?
the second one, when I check_bsd the tools coundn't find my pad cells,and sime of the pad cells' input and output had changed to connect wires that gened by the tools.

Who can give me an advice?
Thank you!!
Click to expand...
 

    HolySaint

    HolySaint

    Points: 2
    Helpful Answer Positive Rating
top_dw_tap_inst

now i use top.v + null_core.v > top_bsd.v

i sim top_bsd.v OK
but when i replace the core module in top_bsd.v with the syned core.v (core_netlist.v) i got sim error:

At time 621995000 : Incorrect output response (xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, expected x0xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
At label" pattern 6217 BSR Vectors EXTEST Shift-DR"

At time 622095000 : Incorrect output response (xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, expected x0xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
At label" pattern 6218 BSR Vectors EXTEST Shift-DR"

At time 656495000 : Incorrect output response (xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, expected x1xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
At label" pattern 6562 BSR Vectors EXTEST Shift-DR"

At time 656595000 : Incorrect output response (xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, expected x1xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
At label" pattern 6563 BSR Vectors EXTEST Shift-DR"

At time 656695000 : Incorrect output response (xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, expected x1xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
At label" pattern 6564 BSR Vectors EXTEST Shift-DR"

At time 656795000 : Incorrect output response (xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, expected x1xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
At label" pattern 6565 BSR Vectors EXTEST Shift-DR"

At time 656895000 : Incorrect output response (xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, expected x1xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
At label" pattern 6566 BSR Vectors EXTEST Shift-DR"

At time 656995000 : Incorrect output response (xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, expected x1xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
At label" pattern 6567 BSR Vectors EXTEST Shift-DR"

At time 657095000 : Incorrect output response (xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, expected x1xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
At label" pattern 6568 BSR Vectors EXTEST Shift-DR"

At time 657195000 : Incorrect output response (xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, expected x1xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
At label" pattern 6569 BSR Vectors EXTEST Shift-DR"

TEST COMPLETED WITH 10 MISMATCHES
Click to expand...
 

extest train .v

Maybe the core logic disturbs bsd somewhere. Dump waveform and see why all are X. Dump output from jtag state machine and other critical jtag control signals, so that you can know what the pattern is doing.

HolySaint said:
now i use top.v + null_core.v > top_bsd.v

i sim top_bsd.v OK
but when i replace the core module in top_bsd.v with the syned core.v (core_netlist.v) i got sim error:
Click to expand...
 

    HolySaint

    HolySaint

    Points: 2
    Helpful Answer Positive Rating
teramax ur edaboard

wizard said:
Maybe the core logic disturbs bsd somewhere. Dump waveform and see why all are X. Dump output from jtag state machine and other critical jtag control signals, so that you can know what the pattern is doing.

HolySaint said:
now i use top.v + null_core.v > top_bsd.v

i sim top_bsd.v OK
but when i replace the core module in top_bsd.v with the syned core.v (core_netlist.v) i got sim error:
Click to expand...
Click to expand...

THQ
i will look carefully
but the five port is adden in the top, maybe the core has some error
 

set_dft_configuration bsd

Hi,
I met the problem about DFT in a design with BSD module. Would you please give me some advice?

Fisrt question: I use the Syn BSD compiler to insert the BSD into my design. I want to know if the BSD module code added to my design can do compile in DC. When I insert the BSD without compile, the check_bsd -verbose will be without violation, but when I compile it, some violations will come out.

My design flow is like your 2nd flow.
1,Compile the core independently
2,Insert DFT by DFT compiler to the core, the coverage_estimate is 97.4%.
3,Insert the BSD into the top level.
4,Exporting the Design to TetraMAX ATPG, this is done in top level, and the setting of it is nearly the same with step 2, but here I add "-exclude_elements [get_cells top_BSR_top_inst]" setting to exclude the BSD module(top_BSR_top_inst) from the scan chain, and write out the protocol file.

The problem came out at the 4th step, when I define the test protocol in top level, the tool can not indentify the scan_path. The scan_path cotains 0 cell. I think there is some thing matter to the BSD module. The BSD add the BSR to every port, and there BSR can not be scaned, so scan_path is broken by these BSR.
How to solved it, please?
In this kind of design, what should I pay more attention to when define the DFT protocol?

The report_scan_path result of top level is;
report_scan_path

****************************************
Report : Scan path
Design : top
Version: B-2008.09-SP4
Date : Wed Jul 15 10:19:20 2009
****************************************

========================================
TEST MODE: Internal_scan
VIEW : Specification
========================================
Scan_path ScanDataIn (h) ScanDataOut (h) ScanEnable (h)
--------------- --------------- --------------- ---------------
chain0 wdata_i_pad[0] (u_0_1/C) rdata_o_pad[0] (u_0_3/I) -

========================================
TEST MODE: Internal_scan
VIEW : Specification
========================================
Scan_path Cell_# Instance_name
--------- ------ -------------
chain0 No scan cells to report


****************************************
Report : Scan path
Design : top
Version: B-2008.09-SP4
Date : Wed Jul 15 10:19:20 2009
****************************************

========================================
TEST MODE: Internal_scan
VIEW : Existing DFT
========================================

========================================
AS SPECIFIED BY USER
========================================


========================================
AS BUILT BY insert_dft
========================================

No scan path defined in this mode.

1
 

no scan cell in the scan path

gaom9 said:
Hi,
I met the problem about DFT in a design with BSD module. Would you please give me some advice?

Fisrt question: I use the Syn BSD compiler to insert the BSD into my design. I want to know if the BSD module code added to my design can do compile in DC. When I insert the BSD without compile, the check_bsd -verbose will be without violation, but when I compile it, some violations will come out.

My design flow is like your 2nd flow.
1,Compile the core independently
2,Insert DFT by DFT compiler to the core, the coverage_estimate is 97.4%.
3,Insert the BSD into the top level.
4,Exporting the Design to TetraMAX ATPG, this is done in top level, and the setting of it is nearly the same with step 2, but here I add "-exclude_elements [get_cells top_BSR_top_inst]" setting to exclude the BSD module(top_BSR_top_inst) from the scan chain, and write out the protocol file.

The problem came out at the 4th step, when I define the test protocol in top level, the tool can not indentify the scan_path. The scan_path cotains 0 cell. I think there is some thing matter to the BSD module. The BSD add the BSR to every port, and there BSR can not be scaned, so scan_path is broken by these BSR.
How to solved it, please?
In this kind of design, what should I pay more attention to when define the DFT protocol?

The report_scan_path result of top level is;
report_scan_path

****************************************
Report : Scan path
Design : top
Version: B-2008.09-SP4
Date : Wed Jul 15 10:19:20 2009
****************************************

========================================
TEST MODE: Internal_scan
VIEW : Specification
========================================
Scan_path ScanDataIn (h) ScanDataOut (h) ScanEnable (h)
--------------- --------------- --------------- ---------------
chain0 wdata_i_pad[0] (u_0_1/C) rdata_o_pad[0] (u_0_3/I) -

========================================
TEST MODE: Internal_scan
VIEW : Specification
========================================
Scan_path Cell_# Instance_name
--------- ------ -------------
chain0 No scan cells to report


****************************************
Report : Scan path
Design : top
Version: B-2008.09-SP4
Date : Wed Jul 15 10:19:20 2009
****************************************

========================================
TEST MODE: Internal_scan
VIEW : Existing DFT
========================================

========================================
AS SPECIFIED BY USER
========================================


========================================
AS BUILT BY insert_dft
========================================

No scan path defined in this mode.

1
Click to expand...

do u sim the pattern gened after bsd insert?
 

Hi, HolySaint
I did not sim the any pattern. I used the TeraMAX to generate the pattern, but because it can not find the scan chain, it failed. I think the BSD inserted to my design (not being compile and is inserted to the gate_netlist with DFT)is right, and the check_bsd result no violation.
But when in the top level, I used the following command to finish the scan chain:

set_dft_configuration -bsd disable -scan enable

set the BSD module and core module dont_touch

compile_ultra-scan -timing -no_autoungroup -no_boundary -top

then define the DFT_top setting

insert_dft

after these commands, the scan chain can be indentified. But the BSD can not work, the check_bsd shown the following violation:

Error: Cannot access Instruction Register during the shift-IR TAP controller state. (TEST-825)
Information: The TDO port tdo is not enabled during the shift-DR TAP controller state. (TEST-865)
Information: Values at the TDO port pad pins:
u24/I = Di, u24/OEN = X, u24/PAD = X. (TEST-1110)
Information: This problem occurred because design input
port test_sea controls the logic. (TEST-901)
...Finished IEEE 1149.1 Compliance Checking.

***************************************************

IEEE 1149.1 Summary

***************************************************

Test Logic Reset Method: Synchronous and Asynchronous(TRST)

16 state elements found in the TAP controller
top_DW_tap_inst/U1_current_state_reg_0_
top_DW_tap_inst/U1_current_state_reg_10_
top_DW_tap_inst/U1_current_state_reg_11_
top_DW_tap_inst/U1_current_state_reg_12_
top_DW_tap_inst/U1_current_state_reg_13_
top_DW_tap_inst/U1_current_state_reg_14_
top_DW_tap_inst/U1_current_state_reg_15_
top_DW_tap_inst/U1_current_state_reg_1_
top_DW_tap_inst/U1_current_state_reg_2_
top_DW_tap_inst/U1_current_state_reg_3_
top_DW_tap_inst/U1_current_state_reg_4_
top_DW_tap_inst/U1_current_state_reg_5_
top_DW_tap_inst/U1_current_state_reg_6_
top_DW_tap_inst/U1_current_state_reg_7_
top_DW_tap_inst/U1_current_state_reg_8_
top_DW_tap_inst/U1_current_state_reg_9_

--------------------------
TAP CONTROLLER DESCRIPTION
--------------------------
State Element Count: 16
State Encoding:
Test-Logic-Reset: 0000000000000001
Run-Test/Idle: 0000000010000000
Select-DR-Scan: 0000000100000000
Capture-DR: 0000001000000000
Shift-DR: 0000010000000000
Exit1-DR: 0000100000000000
Pause-DR: 0001000000000000
Exit2-DR: 0010000000000000
Update-DR: 0100000000000000
Select-IR-Scan: 1000000000000000
Capture-IR: 0000000000000010
Shift-IR: 0000000000000100
Exit1-IR: 0000000000001000
Pause-IR: 0000000000010000
Exit2-IR: 0000000000100000
Update-IR: 0000000001000000
0 cells found in the Instruction Register
0 standard instructions found.
0 user defined instructions found.
NO TEST DATA REGISTER
No boundary scan register

***************************************************

IEEE 1149.1 Violation Summary

***************************************************
1 Boundary scan design Violations found
Violates Rule: 6.1.1a Corresponds to Errors: TEST-825
1 Violations found during extraction of shift register
Violates Rule: 5.2.1d Corresponds to Errors: TEST-865
0

Is there any wrong with the above command?
How to ensure the BSD when the top_level DFT inserting?

Thank you!
Best regards!
 

u mean first u insert bsd
then dft?

I do like this also,but when the bsd inserted, I write a pattern, i simed
erorr toke

u can try to write a pattern
then sim it by nc or vcs
 

Hi, HolySaint
I have tried it. When I used the netlist before insert_dft in top level, it succeeded.
But when I used the netlist afther top level insert_dft, it failed. It shows many unmapped massage.
I think the insert dft will change the circuit even I set all the module to be dont_touch.

Thank you!
Best regards!
 

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