how to choose sampling capacitor

in pipelined adc, how to choose sampling capacitor for every stage? is it limited by thermal noise and DR? but how? what's the optimum value of Cs of S/H and the first stage ?

in order to decrease power consumption, capacitor scaling can be used. but how to decide the scaling factor? and is it same for all stages?

besides, how to choose W and L of the cmos switch? L is Lmin? and how to choose? is there some reasons?

pls help me. thanks all foe reply.

For pipelined ADC, the sampling capacitor size is dictated by the thermal noise.
SNR² = (Vfs²/ 8 )/(kT/Cs)

and SNR = √1.5 2^N
Equating the above equations, gives the Cs = 12kT. 2^(2N)/Vfs²
So for example N=12 and Vfs=1V then Cs=0.833pF
This is the minimum capacitor you need. In practice Cs is like 2-3 times higher.

Capacitor scaling:
For this read "cline gray" paper. They concluded that that optimum scaling factor is reciprocal of interstage gain. For 1.5-b/stage, capacitor scaling factor is 1/2. So if first stage Cs=1pF, then 2nd stage Cs=0.5pF so on and so forth. Ofcourse you can not scale it indefinitely. Why?

Switch:
You choose W/L so that the settling time of switch does not interfere with the settling of the op-amp.

I hope it will help you in deciding the rough parameters.
Regards,
/Noman

for a conservative designer the thermal noise due to switch is 4kT/Cs for sample and amplification phase and fully-differential structure.

the on-resistance of switch slows the speed of amplifier, BWeff=BWorig/(1+gm*Ron).

thanks Usman Hai and jiangxb.but why 4kT/Cs?is it because there are 4 capacitors(2 Cs and 2 Cf , and Cs=Cf)for fully-differential structure and 1.5bit per stage?

besides, there are 9 stages in all, and 8 stages have Cs and Cf(excluding S/H in front end), then how to consider thermal noise of Cs and Cf totally?SNR=S/R,then how to consider S and R respectively?

pls explain to me.thanks.

Added after 3 minutes:

besides, how to understand BWeff=BWorig/(1+gm*Ron) for the on-resistance of switch ?

It seems you are missing the points.
4kt/Cs is because of input referred thermal noise due to capacitor scaling plus noise due to op-amps. That is why jiangxb mentioned 4kT/Cs.

To consider noise due to all capacitors you have to find the input referred noise (as I mentioned above).

Regarding SNR=S/R,then how to consider S and R respectively? I start doubting that you understand basics. SNR is signal to noise ratio. you have to go back and read the basics I guess.

sorry, i made a mistake; SNR=S/N;

as you mentioned above, 4kt/Cs is because of input referred thermal noise due to capacitor scaling plus noise due to op-amps; but why? how to get this result? then the total value of noise power of the adc is kT/Cs or 4kT/Cs or any other value?and why?

pls explain to me clearly.thanks.

the 4kT/Cs is the thermal noise of switch on-resistance only. one kT/Cs comes from the sample phase, and another kT/Cs from amplification phase, so 2kT/Cs. then it is twice due to fully-differential structure. for accuracy calculation during the amplification phase the noise is also the function of gm(opamp's transconductance) and ron(switch's on-resistance), but the conservative and maximum value is kT/Cs. above calculation suit the integrator which can be modified into the amplification function with the integration capacitor reset per cycle.

that means,in rough calculation of SNR for adc, N=kT/Cs, is that right?