vikram789
Member level 3
Determine the minimal clock period TW for the following circuit. Use the following delay values for the flip-flops and gates.
Flip-Flop: 5 ≤ tPFF ≤ 14ns; tsu = 6ns; th = 10ns
Inverter: 2 ≤ tPINV ≤ 12
XOR Gate: 7 ≤ tXOR ≤ 22
Flip-Flop: 5 ≤ tPFF ≤ 14ns; tsu = 6ns; th = 10ns
Inverter: 2 ≤ tPINV ≤ 12
XOR Gate: 7 ≤ tXOR ≤ 22