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Please help me out!!!!

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Tan

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Hello friends,
I am design engineer(VLSI) with 1 yr 8months of exp.
I am planning to shift my job.My skill set is VHDL and fpga design.
However i am not getting any calls as i placed my CV in the job portals.
Please help me out in what areas should i improve or where should i concentrate.How to start my preparation for interviews.your suggestions are highly appriciated.

Thanks and regards
 

Hi Tan

The areas u should be strong are,

1. Digital Design
2. VHDL/Verilog
3. Projects
4. Timing analysis

so these are the basic to be concentrated mainly, apart from this u should prepare FPGA, asic, verification, microprocessors.

Search in this eda site u will find lots of Interview questions discussed, that may help you.
Never give up hope.. keep updating and trying..
cheers.
 

    T

    Tan

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Thank you soo much for your suggestion..

regarding timing analysis can you please elaborate...
 

Its called Static Timing Analysis

I.e regarding Setup and Hold time..

the above link will tell about setup & hold in detail..

also i attach a pdf for sequential circuit timing... hope this will help..
 

yeah i do have that pdf with me.
my doubt is i want to improve my coding style..
i do code in vhdl and there will be no syntax errors but i do not follow the timing analysis.can you please suggest me how to follow the timing analysis correctly..i just code without cosidering the set up or hold time.

i want to learn the coding in such a way that it takes less hardware and code works effectively in all the conditions.
please help..
 

So for that u can refer Xilinx coding guidelines.

in xilinx site if u search u can get the pdf..
 

Thank you so much buddy..
I am going through the pdf's and its really useful...

Added after 1 hours 7 minutes:

I downloaded a document and going through that,I found a concept of RESOURCE SHARING for OPTIMISATION PURPOSE.
Do you have any idea regarding that??How to use that to optimise my design?


cheers
 

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