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A SC at the sampling phase with a MOS transistor as a switch is shown in Fig3. When the switch is ON, there is an amount of charge accumulated in the conducting channel of the transistor. The accumulated charge is given by: (eq
shown below)
When the switch turns off, this charge is injected to the either direction and part of the charge (ΔQ) is dumped into the capacitor CS. The charge ΔQ results in an error voltage of ΔQ/CS on CS. In a fast switching-off condition when the falling time of the control clock is very fast, the transistor channel disappears quickly. In practice, the charge ΔQ is hardly can be predicted precisely.
When the switch turns off, this charge is injected to the either direction and part of the charge (ΔQ) is dumped into the capacitor CS. The charge ΔQ results in an error voltage of ΔQ/CS on CS. In a fast switching-off condition when the falling time of the control clock is very fast, the transistor channel disappears quickly. In practice, the charge ΔQ is hardly can be predicted precisely.
I have also read something like this too.
I have known that, there are charge that must be dumped when clock is turned to '0'.
but, a question comes out that I don't know the fraction of charge that dumped to Drain and that dumped to Source. and how the impedance in Drain and Source will interference.(the impedance can be same/different between Drain and Source)
clock feedthrough and charge injection are different. Clock feedthrough means clock signal change at the gate node lead to a change in drain/source voltage through Cgd and Cgs coupling.
And charge injection means the charge is squeezed into/absorbed
from drain/source during channel forming or disappearing.
When the switch turns off, this charge is injected to the either direction and part of the charge (ΔQ) is dumped into the capacitor CS. The charge ΔQ results in an error voltage of ΔQ/CS on CS. In a fast switching-off condition when the falling time of the control clock is very fast, the transistor channel disappears quickly. In practice, the charge ΔQ is hardly can be predicted precisely.
I have also read something like this too.
I have known that, there are charge that must be dumped when clock is turned to '0'.
but, a question comes out that I don't know the fraction of charge that dumped to Drain and that dumped to Source. and how the impedance in Drain and Source will interference.(the impedance can be same/different between Drain and Source)
It is hard to model the charge dispersion ratio, but generally it is assumed that half of the charge is transferred to source and the other half to drain. I think the effective length of channel depending on the operation mode is also a factor on that because in saturation charge is accumulated to source greater than drain(meaning that channel length modulation).
yepp.I agree with you,clock feedthrough is a instantaneous process of capacitors charge redistrubution for KVL satisfcation,it is a direct result of clock transition and its timescale is on the order of the clock edge transition.But the charge injection is the process of mos switch turn on/off,and its sucking/squeezing charge from/to source and drain node，which is a indirect result of clock transition and switch on/off,maybe it is happens later and slower than clock feedthrough.There is subtle difference in two here.
correct me if I'm wrong pls
leo_o2 said:
clock feedthrough and charge injection are different. Clock feedthrough means clock signal change at the gate node lead to a change in drain/source voltage through Cgd and Cgs coupling.
And charge injection means the charge is squeezed into/absorbed
from drain/source during channel forming or disappearing.
For partially removing the effect of charge injection we put two swithes of half the size (of switch) on boths sides of the switch with gate being connected to opposite polarity. This way we try to absorb the exact charge when the switch is turned off of supply the exact chrge when it is turned on. Though the distribution of chrge between source anmd drain maynot be equal, but this does reduce the error.
Charge injection is, in a sense, the imbalance of clock
feedthrough.
Cancellation schemes often work well at a centered input
common mode voltage, but to work well across the entire
input range the driving clock voltages relative to signal,
need to be controlled. Otherwise you have mismatched
overtravel voltages hence mismatched charge from the
gate drives. But this is messy to fix and maybe a first order
compensation is good enough, especially if the signals are
AC coupled and restored to a VDD/2 common mode.
Thank you for your answer but... it doesn't seem to be clear for me. Do you have any schematics or references?
By the way, I'm looking for dummy sw cancellation, bottom plate sampling... but I think that for a better design, a good sizing of the troubles could be a good way for capacitor and/or dummy sw sizing.
Indeed yes you can quantify the amount of charge injected on either terminal of the switch by calculating the dynamic impedance seen on each of these terminals.
Indeed yes you can quantify the amount of charge injected on either terminal of the switch by calculating the dynamic impedance seen on each of these terminals.
sure! but... it also depends on how fast are the clock edges! Fast edge = 50/50 charge injection on drain and source. Lowest edge, the charges are injected on the lowest impedence (ie input source). The equation for hand calculation has a lot of unknow variables...
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