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PLL transistor-level design

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liuyonggen_1

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i am a beginner in the field of PLL

could someone show me some papers about the transistor-level design of the PLL,such as PFD, OSC and so on?
thanks a lot!
 

Dear liuyonggen_1:

You can reference it.

mpig
 

Hi

Search IEEE and you should find lots of papers.
Here I attached some for you to kick start

"A PLL clock generator with 5 to 110Mhz lock range for microprocessor", I.A. Young, 1992
"A power efficient wide range PLL", T.C. Chen, 2002
"Low jitter and process independent DLL and PLL based on self-biased techniques", J.C. Maneatis, 1996 (one of golden papers in PLL)
"A 2-5GHz low jitter 0.13um CMOS PLL with dynamic current matching charge pump and a noise attenuating loop filter", A. Maxim, 2004
"Design of a low jitter 1GHz Phase locked loop for digital clock generation, W. Rhee, 1999
 

who can provide some papers on the phase noise on the VCO?
 

Have anyone design of dual-path PLL transistor-level?
 

who can give the design procedure for PLL?

thanks
 

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