how to correct this error?

use set -loop_iteration_limit xx to iterate more.

while compiling my program written for modular division & montgomery modular multiplication in verilog, i often get the following error...

----Can not simplify operator REM.
----Loop has iterated 64 times. Use 'set -loop_iteration_limit XX' to iterate more.

can u tell me what it is?

loop_iteration_limit

send me ur code

set -recursion_iteration_limit xx

Code for montgomery modular multiplication
module mont( x, y, m, n, z);
input [3:0] x;
input [3:0] y;
input [3:0] m;
input [3:0] n;
output [3:0] z;
reg [3:0]a;
reg [3:0]v;
reg [3:0]p;
reg [3:0]q;
reg [3:0]z;
reg [3:0]u;
reg [7:0]t;
always@(x,y)
begin
assign a = y;
assign v = x;
assign p = n;
end
initial
begin
assign u = 0;
end
always @(x,y)
while (p!= 0) begin
if (a % 2 == 0)
assign q = 0;
else
assign q = 1;
assign a = (a-q)/2;
assign t = ((u+(q*v))/2) ;
assign u = t / 2 % m;
assign p = p-1;
end
always @(x,y)
if (u >= m)
assign z = u-m;
else
assign z = u;
endmodule

Code for Modular division

module moddiv(x, y, n, z);
input [3:0] x;
input [3:0] y;
//input [3:0] m;
input [3:0] n;
output [3:0] z;
reg [3:0] z;
wire [3:0] m;
reg a, b, u, p;
reg v, l;
reg t, q;
always @(x,y)
begin
assign a = y;
assign b = m;
assign u = x;
assign p = n;
end
initial begin
assign v = 0;
assign l = 0;
end
always @(x,y)
while (p != 0) begin
while (a%2 == 0) begin
assign a = a/2;
assign u = u/2 % m;
assign p = p-1;
assign l = l-1;
end
if (l<0) begin
assign t = a;
assign a = b;
assign b = t;
assign t = u;
assign u = v;
assign v = t;
assign l = -l;
end
if ((a+b)%4 == 0)
assign q = 1;
else
assign q = -1;
assign a = (a + q * b)/4;
assign u = (u + q * v)/4 % m;
assign p = p-1;
assign l = l-1;
end
always @(x,y)
if (b == 1)
assign z = v;
else
assign z = m-v;
endmodule

Here for representing mod M, I have used % M; is there any other way to represent mod M.
or is there any way to correct this error?

set -loop_iteration_limit xx

Hello,

I see, that the loop iterates infinitely. That would be also an issue in procedural programming with a computer, but could be syntactical correct code. In HDL it's also physical impossible, cause a parallel logic structure has to be inferred from a iterative loop. This would be equivalent to an infinite gate count.

I have no time now, to look deeper into the code, it may be a simple coding error.

Regards,
Frank

set loop_iteration_limit

Hello,

examinating the moddiv code more thoroughly, I see that both iterative loops
have each no effective stop criterion, they may run endlessly, depending on input values. That means, that code can't be synthesized for hardware. I must admit, that I had difficulties to see an algorithm behind the code, thus I was unable to find a possible coding error. But if the mathematical method intended to realize in this code is applicable in general, it could also be coded.

May be the issue is by a basic misunderstanding of verilog construct properties?
Can we have a brief description of the algorithm or a literature reference?

Regards,
Frank

use set -loop_iteration_limit xx to iterate more

Thankyou
ALGORITHM FOR MODDIV

INPUTS: m : 2^(n-1) < m < 2^n, gcd(m,2)=1 & prime
x, y : 0 <= x< m, 0<y<m
OUTPUT : z = x/y mod m
ALGORITHM
a := y; b:=m; u :=x;
v := 0; p :=n; l :=0;
while p != 0 do
while a mod 2 = 0 do
a:= a/2; u := u/2 mod m;
p :=p-1; l :=l-1;
endwhile
if l<0 then
t:=a; a:=b; b:=t;
t :=u; u :=v; v :=t;
l := -l;
end if
if (a+b) mod 4 = 0 then q :=1;
else q := -1;
a := (a + q *b)/4;
u := (u +q*v)/4 mod m;
p :=p-1;
l :=l-1;
endwhile
if b =1 then z :=v;
else /* b= -1*/
z := m-v;

Added after 30 minutes:

ALGORITHM FOR MONTGOMERY MODULAR MULTIPLICATION

inputs : m : 2 ^(n-1) < m < 2^n, gcd(m,2) = 1;
x , y : 0 <= x, y <m
output : z = xy2^n mod m
ALGORITHM
a :=y; u :=0; v :=x; p := n;
while p != 0 do
if a mod 2 =0 then q := 0 else
q := 1;
a :=(a-q)/2; u :=(u + qv)/2 mod m;
p := p-1;
endwhile
if u >=m then z = u-m;
else
z:=u;

being a beginner in verilog I feel difficult in this correcting error.
I also tried certain other algorithms for this modular division & montgomery modular multiplication which also resulted in the same error