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Slew Rate does not depend on current of output stage. If we are using two-stage amplifier, Slew Rate = Itail/Сс!!! Another way to inrease Slew Rate - design SlewBoost schem
If you really want large slew rate to charge capacitance load, use class AB output stage. Or you will have to increase the bias current. I remember there are some slew rate boost techniques. Let us know if you find some.
Hi every body
i have big problem with the settling time also, the problem i am designing sample and hold work with 50MS/s, the ota has Fu=229Mhz, Phase 76, but the settling time =50ns.
so i need to make it 15ns. could some one help me and what is the SlewBoost schem?
regards
What type of amplifier are you using? Try using single-stage-OTA. If gain insufficiently large, use gain boost technique. In case of single-stage-OTA all are simple: If settling is long, you need large load capacitance, if Slew is long, Itail must be higher
Allen.
6.1 Design of CMOS opamp
Page 248
"The Slew Rate is generaly determinated by the maximum current available to charge or discharge a capacitance. Normally,slew rate is not limited by the output,but by the current soutcing/sinkiing capability of the firts stage"
Sorry for the misleading statement, yes if it were 2 stage opamp with compensation, then it should be the biasing current of the first stage need to be increased in order to charge/discharge the compensation capacitor faster, whereby if it were a single stage opamp then the biasing current depend on the charge/discharge of the load capacitor.
Yes, increase the standing current or the current drive capability of the stage which actually limits the slew rate ...
That's normally the stage which drives the Cdom. This stage should also be able to source and sink the same amount of current, otherwise you get an asymmetric slew rate.
But if you still have plenty of phase margin you could also increase the transconductance gain or de-compensate the amplifier by another means. But this would also alter the settling time because of excessive ringing.
In switch capacitor circuit, settling is composed of two steps: slewing and linear settling. Normally, slewing is something we try to avoid. I have a hard time understanding it. Since during slewing, all of the tail current is used to charge the load, it will speed up the settling. Why we still try to avoid slewing?
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