What is the relationship between ESD and latch up?

Is placing ESD structure more susceptible to latch up? Particularly ESD to core and latch-up relationship.

Any reference website and paper is welcome.

THANX

plz make your question more clear.what do you mean?
in my opinion,there is no tight relation between the ESD and latch up.
ESD is to protect the core;Latch-up is because of the parasitic effect of the transistors.

ee484 said:

Is placing ESD structure more susceptible to latch up? Particularly ESD to core and latch-up relationship.

Any reference website and paper is welcome.

THANX

Click to expand...

hi
yes, you are right. as i know, like SCR structure, it will actrually induce latch up.
so when design such structure, you must be careful. in normal mode, the latch up caused by esd protection ckt will not happen, but when esd test or a large electro-static charge inject, the latch up is used to discharge it.
jeff

latchup is opening parasitic thyristor structure - as the "up" says
device has trouble to switch it off again. Then the generated heat kills the structure.

ESD protection is designed to protect the internal circuitry by dissipating the ESD pulse to either VDD or GND i controlled fashion.

The closest relation between those two is that badly designed ESD protection can cause latchup.

In planar CMOS fabrication, there is a parasitic bipolar (PNP) transistor that is formed between the drain, N-well, and substrate of a CMOS device. Under normal circumstances, this device is 'off', because the voltage due to charged particles in the N-Well region w.r.t. the substrate is too low to forward-bias this parasitic base-emitter junction. However, if enough charge builds up in the N-Well region (either because of insufficient contacts between the power supply (Vdd) rail and the NWell region, or because of an uncharacteristically high inrush of charge carriers into the region like that associated with an ESD discharge) then this vertically-oriented, parasitic transistor turns on and begins to conduct current between the drain and the substrate. With virtually no resistance across the silicided drain region, the current quickly and permanently destroys the device.
That is why most technologies will require a silicide block over the drain (and source) region - to add series resistance to the leg that is attached to the pad. This series resistance serves two purposes - one is to limit the current through the 'turned-on' parasitic transistor, and the other is because this forms something of a voltage divider which knocks down the potential that is applied to the CMOS device terminals during an ESD event.
I hope this helps.

ESD devices are usually where latchup rules are imposed,
because they are pin-exposed and large abnormal current
could be injected. The presumption is that the core
has no pin access (other than supplies) and the tie rules
there suffice.

ESD devices do not cause latchup, they are only the
handiest victimes.