Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

FPGA <-> SATA disk?

Status
Not open for further replies.

staraimm

Full Member level 2
Joined
Oct 21, 2006
Messages
133
Helped
5
Reputation
10
Reaction score
1
Trophy points
1,298
Activity points
2,178
fpga sata

I want to use a FPGA chip to read/write a SATA disk. But due to the high speed of the SATA protocol, it seems very difficult to do that. Can anybody give me suggestion?
 

sata fpga

Hi
please see this link.
I think there is no problem!
**broken link removed**
 

fpga sata controller

The prototype board "SMT387-VP20-6" does not actually use the FPGA chip to realize the SATA protocol. In fact, it realizes two Serial ATA Disk Interface, using Silicon Image Serial ATA Link 3512 device.
 

sata interface chip

Some Xilinx Virtex FPGA families have multi-gigabit serial transceivers (also called RocketIO or GTP or MGT) that can support SATA, PCIe, SFP, and other fast stuff. Some Xilinx development boards such as the ML506 include SATA host ports connected directly to the FPGA with no external controller chip. You could download the board's documentation:
**broken link removed**

The "Virtex-5 RocketIO GTP Transceiver User Guide" gives low-level details for configuring the Virtex-5 transceivers for 1.5 and 3.0 gigabit SATA.
**broken link removed**

Of course, the FPGA silicon provides only the serial transceivers, so you'll need to implement the higher-level protocol controller in the FPGA fabric, or use someone's IP.
 

    staraimm

    Points: 2
    Helpful Answer Positive Rating
serial ata fpga

Hi All,

I am working PCI Express design in our project. I am using the GTP core which is existing the Pci end point interface design is connected diff clock interface. We are not yet recevie the clk properly. The ref clock we are using to generate the core is 100Mhz , 4 lane. Pins mapped from fpga Pad are P4,P3. Virtex-5VLX device.

By test i did, i realized that the End point trn_clk is not come.

1. How can check whether End point module is receving the clock properly or not ?

2. How to solve the clock issue.

I hope, i can get a solution for my design issue. Ple help me.
 


sata interface chips

In addition to echo47 note, ML501,2,3 and ML505,506 has direct SATA interface. These boards data are available at Xilinx.com and they do not need any extra devices to interface SATA
 

sata fpga controller

well, as far as I know, it should also be possible with Virtex-II Pro, so, if Virtex-5 is not available , you can use that one instead.
 

virtex-5 sata

VirtexII Pro can not support OOB signaling. It can't use for SATA PHY.
Virtex4FX can't pass SATA Compliant test.
Virtex5LXT and Virtex5SXT are only devices that fully complaint with SATA1/2.
 

    staraimm

    Points: 2
    Helpful Answer Positive Rating
virtex5 sata

elektrom, so what's your suggestion to build SATA host/device using a fpga chip?
 


Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top