Question and answers on Positive/Negative Skew

Skew Topic

Hi all,

Whether Positive skew is good for Setup? How?
Negative skew is bad for setup?
Positive skew is bad for hold?
Negative skew is good for hold?
Please tell me with some examples?

In STA report, if we find any hold violation, it can be remedied by adding buffers? Whether it will cause setup violation? Then how much to add and on what basis?

Hold can also reduced by decreasing clock uncertainty in design?
Please tell me these doubts?


Thanks

Re: Skew Topic

hi Energeticdin,

my 2 cents to your queries.

Whether Positive skew is good for Setup? How?
positive skew is similar to useful skew , it is nothing but delaying capture clock by skew value correct than the normal launch clock value when ever you delay the capture clock surely you gain that my margin which can reduce in your setup violation. If you want to visualize properly , you can think like if you have more period then surely setup violation will reduce correct. it is similar concept.


Negative skew is bad for setup?
similar to my earlier answer here you are reducing the capture clock.

Positive skew is bad for hold? Negative skew is good for hold?

for example: FF1 --> FF2 --> FF3
case 1: All FF[flip flop ] has zero skew.
analysis: You have a setup violation path from FF1 to FF2.
Work around : Trying to optimize the datapath from FF1 to FF2 , you cannot do it , as the path is already optimized. Now what is the only option left is playing safely rather marginally with clock.
So you are planning for skewing the capture flip flop clock that is FF2, delaying , so assume you met with the setup violation across FF1 to FF2.

Another scenario comes, you had delayed your FF2 more , so you have a hold violation to FF3.
hope the concept is clear.

In STA report, if we find any hold violation, it can be remedied by adding buffers? Whether it will cause setup violation? Then how much to add and on what basis?
Assuming you have hold violation, you cannot go on apply on adding buffers on the data path. Before doing this you need to check the setup margin across the endpoint and see .
There could be scenario's where in path passing through a cell A you have setup and path passing through cell B input you have a hold violation, you have to apply specify back-trace and apply to that specifi inputs only and not on the endpoint register straight away.

Uncertanity you are adding is for your margin's / jitter / process variations and things like that, reducing uncertanity is not a correct option to reduce your violation count. It is like taking from your saving's account and spending!!!

These links could help you to get the concepts better
https://www.vlsichipdesign.com/timing_closure.html
https://www.vlsichipdesign.com/check_design.html

Praise the Lord.

Best regards,
vlsichipdesigner
https://www.vlsichipdesign.com