lagos.jl
Member level 1
ivpcell cadence
Hello all; it's me again begging for some help!
I am trying to learn how to do LVS by following the "Cell Design
Tutorial" on the Cadence documentation, which uses a very simple 2-
input mux as example. Everything went fine up to the DRC, but I
started having trouble on the LVS phase. The LVS failed with the
following errors (si.log):
...
Begin netlist: Nov 7 03:59:41 2007
view name list = ("auLvs" "extracted" "schematic")
stop name list = ("auLvs")
library name = "tutorial"
cell name = "mux2"
view name = "extracted"
globals lib = "basic"
Running Artist Flat Netlisting ...
*WARNING* invalid cell view -- 0(unknown)
*WARNING* invalid cell view -- 0(unknown)
global error:
Cannot find switch master cell for instance +13 in cellView (mux2
extracted) from viewlist 'auLvs extracted schematic ' in library
'tutorial'.
...(same error repeated for every mos instance in the extracted
view)...
Research on the web lead me to think that this was due to netlisting
errors. When I look at the properties of the transistors in the
extracted view, they all are "ivpcell" views and not "auLvs". Despite
I don't yet understand view lists, I tried creating a .simrc file with
the following contents:
lvsLayoutViewList = '("ivpcell" "auLvs" "extracted" "schematic")
lvsLayoutStopList = '("ivpcell" "auLvs")
lvsSchematicViewList = '("auLvs" "schematic")
lvsSchematicStopList = '("auLvs")
lvsLayoutVersionName = nil
lvsSchematicVersionName = nil
Now the "invalid cell view" warnings are gone, but then the LVS fails
with other errors:
Begin netlist: Nov 7 04:12:16 2007
view name list = ("ivpcell" "auLvs" "extracted" "schematic")
stop name list = ("ivpcell" "auLvs")
library name = "tutorial"
cell name = "mux2"
view name = "extracted"
globals lib = "basic"
Running Artist Flat Netlisting ...
*Error* Cell: pfet in library: sample is missing a simInfo section
in it's CDF for the current simulator.
*Error* artIsCallablep: argument #1 should be either a string or a
symbol (type template = "S") - nil
error in instance path /+13:
Error in evaluating property value: 'ancNetlistFileInstOutput()'.
...(same error repeated for all pmos instances)...
*Error* Cell: nfet in library: sample is missing a simInfo section
in it's CDF for the current simulator.
*Error* artIsCallablep: argument #1 should be either a string or a
symbol (type template = "S") - nil
error in instance path /+6:
Error in evaluating property value: 'ancNetlistFileInstOutput()'.
...(same error repeated for all nmos instances)...
One last weird observation. All the instances in the extracted view
belong to library named "sample", and not to the "pCells" library, as
(I guess) one would expect. Transistor cells in the the "sample" lib
don't have 'auLvs' views, while the ones in the "pCells" lib have both
'auLvs' and 'ivpcell' views. ...Clueless about which one is the
correct one nor what are the differences between these two types of
views... *sigh*
It seems I am missing some basic configuration. BTW, I already checked
the 'CDS_Netlisting_Mode' is (properly?) set to 'Analog'. Any ideas on
what could be the problem? Thanks in advance for any help, and sorry
for the repeatedly long posts.
Regards,
Hello all; it's me again begging for some help!
I am trying to learn how to do LVS by following the "Cell Design
Tutorial" on the Cadence documentation, which uses a very simple 2-
input mux as example. Everything went fine up to the DRC, but I
started having trouble on the LVS phase. The LVS failed with the
following errors (si.log):
...
Begin netlist: Nov 7 03:59:41 2007
view name list = ("auLvs" "extracted" "schematic")
stop name list = ("auLvs")
library name = "tutorial"
cell name = "mux2"
view name = "extracted"
globals lib = "basic"
Running Artist Flat Netlisting ...
*WARNING* invalid cell view -- 0(unknown)
*WARNING* invalid cell view -- 0(unknown)
global error:
Cannot find switch master cell for instance +13 in cellView (mux2
extracted) from viewlist 'auLvs extracted schematic ' in library
'tutorial'.
...(same error repeated for every mos instance in the extracted
view)...
Research on the web lead me to think that this was due to netlisting
errors. When I look at the properties of the transistors in the
extracted view, they all are "ivpcell" views and not "auLvs". Despite
I don't yet understand view lists, I tried creating a .simrc file with
the following contents:
lvsLayoutViewList = '("ivpcell" "auLvs" "extracted" "schematic")
lvsLayoutStopList = '("ivpcell" "auLvs")
lvsSchematicViewList = '("auLvs" "schematic")
lvsSchematicStopList = '("auLvs")
lvsLayoutVersionName = nil
lvsSchematicVersionName = nil
Now the "invalid cell view" warnings are gone, but then the LVS fails
with other errors:
Begin netlist: Nov 7 04:12:16 2007
view name list = ("ivpcell" "auLvs" "extracted" "schematic")
stop name list = ("ivpcell" "auLvs")
library name = "tutorial"
cell name = "mux2"
view name = "extracted"
globals lib = "basic"
Running Artist Flat Netlisting ...
*Error* Cell: pfet in library: sample is missing a simInfo section
in it's CDF for the current simulator.
*Error* artIsCallablep: argument #1 should be either a string or a
symbol (type template = "S") - nil
error in instance path /+13:
Error in evaluating property value: 'ancNetlistFileInstOutput()'.
...(same error repeated for all pmos instances)...
*Error* Cell: nfet in library: sample is missing a simInfo section
in it's CDF for the current simulator.
*Error* artIsCallablep: argument #1 should be either a string or a
symbol (type template = "S") - nil
error in instance path /+6:
Error in evaluating property value: 'ancNetlistFileInstOutput()'.
...(same error repeated for all nmos instances)...
One last weird observation. All the instances in the extracted view
belong to library named "sample", and not to the "pCells" library, as
(I guess) one would expect. Transistor cells in the the "sample" lib
don't have 'auLvs' views, while the ones in the "pCells" lib have both
'auLvs' and 'ivpcell' views. ...Clueless about which one is the
correct one nor what are the differences between these two types of
views... *sigh*
It seems I am missing some basic configuration. BTW, I already checked
the 'CDS_Netlisting_Mode' is (properly?) set to 'Analog'. Any ideas on
what could be the problem? Thanks in advance for any help, and sorry
for the repeatedly long posts.
Regards,