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How can we design a divide by three clk with 50% duty cycle ?

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vlsi_freak

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Hello..

How can we design a divide by three clk with 50% duty cycle.

If anyone having any doc's please share..

Thanks
 

Re: Clk Divider

Take 2 shift registers, each 3 bits. Make each shift register a ring counter, so that Q[2] feeds ino D[0].
Reset each of this 3 bit ring counters to a value of Q2Q1Q0 = 110.
When not in reset, it will work as a ring counter.
Now make one ring counter work on +ive edge of clk and the other on -ive edge.

Now your divby3clk is AND of Q[2]s taken each from the 2 ring counters working on opposite clock. In fact you can take the o/p from an Q pair, like Q[1]s or Q[0]s
Kr,
Avi
http://www.vlsiip.com
 

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