Mercury
Member level 3
Hello!
I am a beginner at Xilinx 9500 series CPLDs using Webpack 5.2. I wrote the attached file as a pwm comparator/generator with input latch. The problem is that when I synthesize it I get a warning: found 1 bit latch for signal PWM. Also when I run the fitter report I get a "red X" left of the "fitter report". So I would like to know what I am doing wrong.
Let me expalin a bit more the pwm comparator. In the Cin input I will bring an 8 bit counter output, and at Din the 8 bit pwm value. The concept is as follows:
- the comparator sets pwm output when the Cin reaches top (255).
- The pwm output is cleared when the Din ( or the latched signal data ) equals Cin. This is more or less it.
I thank you in advance for your answer.
Best regards
George Mercury
Sorry, I have tried to attach the file, but I've had no sucess:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Comparator is
Port (
pwm: out std_logic;
str: in std_logic;
rst: in std_logic;
Din: in std_logic_vector(7 downto 0);
Cin: in std_logic_vector(7 downto 0)
);
end Comparator;
architecture comp of Comparator is
signal data: std_logic_vector(7 downto 0);
signal top: std_logic;
signal equ: std_logic;
begin
p00: process(str)
begin
if str'event and str = '1' then
data <= Din;
end if;
end process;
p01: process(top,equ,rst)
begin
if rst = '0' then
pwm <= '0';
elsif top = '1' then
pwm <= '1';
elsif equ = '1' then
pwm <= '0';
end if;
end process;
equ <= '1' when data = Cin else '0';
top <= '1' when Cin = "11111111" else '0';
end comp;
I am a beginner at Xilinx 9500 series CPLDs using Webpack 5.2. I wrote the attached file as a pwm comparator/generator with input latch. The problem is that when I synthesize it I get a warning: found 1 bit latch for signal PWM. Also when I run the fitter report I get a "red X" left of the "fitter report". So I would like to know what I am doing wrong.
Let me expalin a bit more the pwm comparator. In the Cin input I will bring an 8 bit counter output, and at Din the 8 bit pwm value. The concept is as follows:
- the comparator sets pwm output when the Cin reaches top (255).
- The pwm output is cleared when the Din ( or the latched signal data ) equals Cin. This is more or less it.
I thank you in advance for your answer.
Best regards
George Mercury
Sorry, I have tried to attach the file, but I've had no sucess:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Comparator is
Port (
pwm: out std_logic;
str: in std_logic;
rst: in std_logic;
Din: in std_logic_vector(7 downto 0);
Cin: in std_logic_vector(7 downto 0)
);
end Comparator;
architecture comp of Comparator is
signal data: std_logic_vector(7 downto 0);
signal top: std_logic;
signal equ: std_logic;
begin
p00: process(str)
begin
if str'event and str = '1' then
data <= Din;
end if;
end process;
p01: process(top,equ,rst)
begin
if rst = '0' then
pwm <= '0';
elsif top = '1' then
pwm <= '1';
elsif equ = '1' then
pwm <= '0';
end if;
end process;
equ <= '1' when data = Cin else '0';
top <= '1' when Cin = "11111111" else '0';
end comp;