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-> propagation delay of source Flop
->Combinational delay between source Flop and destination Flop
->setup time of destination flop
->skew between flop
Well, agreed with wot uditkumar1983 has written. Well here is a formula if you are interested:
Fmax = 1/(Tsu+Tpd+Ttc)
Well make it simple I have not considered skew.
Where
Tsu = Setup Time of FF
Tpd = Propagation delay of the FF
Ttc = Delay of the combinational logic between the FFs.(This would be of the worst combi delay in your design)
Kr,
Avi http://www.vlsiip.com
Hi, I have given this answer a while ago, but I would again write(cut+paste) it here:
Hold time does not count towards the frequency of operation.
Fmax = 1/(Tsu+Tpd+Ttc)
If you look at a cmos circuit of a flip flop, then you will see that Tpd, that is propagation delay of an FF, i.e delay from Clock to Q output, is always greater than hold time. In fact it can be shown that Tpd is always Thold + something. So it 'encapsulates' the hold time. So once Tpd is considered in calculating Fmax, hold time is automatically taken care of.
If you consider a hypothetical situation where Tpd is less than hold time, then Fmax will be calcualted using thold as well. But this is not possible in a normal circuit of a flip flop.
Hence hold time is never taken into account while calculating Fmax
Hope this helps
Kr,
Aviral Mittal http://www.vlsiip.com
Jitter is the temporal variation in the clock signal, and effects the Pulse width unlike the skew,Jitter needs to be consider to calculate the Tmax for worst case of Jitter where first clock pulse had its pulse width greater and the next smaller.:arrow:
Maximum frequency calculation is unique calculation for each ckt. we can simply define it as reciprocal of critical path (maximum) delay other than pure combinational path delay.
u can design your own problems and u can solve it.
remember that to solve STA problems better solve by drawing waveforms than simply using equations it avoids confusion
Hi, I have given this answer a while ago, but I would again write(cut+paste) it here:
Hold time does not count towards the frequency of operation.
Fmax = 1/(Tsu+Tpd+Ttc)
If you look at a cmos circuit of a flip flop, then you will see that Tpd, that is propagation delay of an FF, i.e delay from Clock to Q output, is always greater than hold time. In fact it can be shown that Tpd is always Thold + something. So it 'encapsulates' the hold time. So once Tpd is considered in calculating Fmax, hold time is automatically taken care of.
If you consider a hypothetical situation where Tpd is less than hold time, then Fmax will be calcualted using thold as well. But this is not possible in a normal circuit of a flip flop.
Hence hold time is never taken into account while calculating Fmax
Hope this helps
Kr,
Aviral Mittal index
hi..
sir I'm the begineer of vlsi design...According to Diagram i attached here..
with respect to the propagation delay.ie the minimum/maximum time(t3-t2) for the input to propagate and influence the output. the prop delay is less than holdtime(t4-t2)...is that true sir..or else the diagram shown here is wrong...
then with respect to definitions,the the time durations of setuptime(t2-t1),and others are correct know...make it clear sir..
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