could I use a floating pwell

esd floating well

I am design a very low current project. I use a schematic like attachment. At high temperature ,the leakage of the mos switch from N+ drain to pwell is very high, causing the voltage on the capacitor draw down because it sample every 50ms.
So I decide to use a switch to control the pwell . when sample the signal, I turn on the switch to make the bulk and the source have a same potential . When hold ,I shut down the switch, making the pwell floating. So the leakage is cutoff.
I wonder wether there is any problem in this ckt. The ckt is chip inside, it won't face any ESD problem.

Hello bluesmaster,

The structure seems fine to me. But, I am worried about latch up in such a structure. You have both the MOS devices sharing the same epi island. That means that the epi forms a huge collector of a parasitic npn (whose base is floating). therefore, everytime you have voltage spikes on the epi potential it can possibly be capacitive coupled to the base and raising its potential and injecting carriers into the epi island. That is, you have inadvertant well charging.

You should ensure that the well cannot be charged by any means when it is floating.


- Transbrother

You are right. Any spike on the pwell will cause the highest of the Nepi to the N+ diffusion. But my N+ will be 0.3 to 1.2 v. It is not easy to couple the pwell more than 0.2v higher. Maybe a capacitor from pwelll to a clean power will improve the
immunity.

The floating well has the potential for many problems, I have listed several here. If any problem can not be mitigated, the floating well switch can not be used (I would not guarantee that all of the potential problems are even listed here):

1- Potential for latch-up. The N-P-N formed by the structure is half of an SCR latch. By having the floating well, you introduce the possibility of triggering the SCR and causing latch-up. Depending upon your power source, this could be a catastrophic event, damaging the chip and potentially even damaging the power supply or test equipment. There are techniques to mitigate this in the literature, but I am not sure if any of these techniques work for the floating well.

2- Varying leakage condition. Because the well voltage is not defined in the off state, there is a strong potential for the diode (D1) to be slightly forward biased, leading to a leakage from the capacitor that is sometimes present and sometimes absent.

3- Capacitive coupling. The capacitance of the N+/Pwell diode from the source to the well can allow signal to AC couple from Vin to the well. The N+/Pwell diode from the drain to the well can then couple from the well to Vout, providing a direct path for AC signal from Vin to Vout. If Vin is changing when Vout is holding, this can cause problems.

4- Channel charge injection. It is likely that the well node will be higher impedance than the Vout node, which means that much of the channel charge for the secondary switch will be directed to Vout.

5- If the Pwell becomes a higher voltage than the epi voltage (due to charge injection from Vin, for example), there will be a biploar with well as the base, epi as the emitter and N+ drain as the collector. The collector current will run from the Vout voltage, and can pull considerable charge from Vout without taking much charge from the well due to the beta multiplication of the bipolar, leading to the wrong voltage on Vout.

Due to the amount of issues with the floating well, I would strongly advise against using it without very careful consideration of all of the potential issues that the floating well could produce

nice answer JPR; I agree with you.

in this sense, we should always avoid to use floating well???
but i read from a textbook in which it does use a floating well, i don't understand the reason as you can see from the picture below



if you can't see it clear ,pls refer to:
https://obrazki.elektroda.pl/7_1184997919.jpg

Actually what we should take away with us is that for critical ckts that carry signal voltage/current such as the one discussed in this topic, there could be potential issues such as inadvertent well charging.

For I/O protection, this requirement is not that strict. However, I would still not use floating wells in such a scheme.

To prcken:
the well of the pmos maybe connect to the vdd through series of diodes or connected to a higher vdd to improve the ESD level.I don't think the well is just floating.If so ,it won't pass a drc check.

thx 4 your discussion

it is a good ideal

Very good answer by JPR