atferrari
Full Member level 4
- Joined
- Jun 29, 2004
- Messages
- 237
- Helped
- 7
- Reputation
- 14
- Reaction score
- 3
- Trophy points
- 1,298
- Location
- Buenos Aires - Argentina
- Activity points
- 1,996
Micro 18F452
I have implemented a clock, with the module CCP1 (compare mode) against TMR1 (counter mode).
To get a fixed duty cycle in RC2 pin, upon matching TMR1, the ISR loads alternatively two values in the CCPR1H:L registers.
Above ISR is high priority. Another one, running in low priority have no problems to coexist.
Regarding the latency, in the manual, I read:
For external interrupt events, such as the INT pins or the PORTB input change interrupt, the interrupt latency will be three to four instruction cycles.
The exact latency is the same for one or two-cycle instructions.
Having run all this through MPSIM I found a variation in the time elapsed between successives entries to the ISR, with the adequate allowance for the actual value loaded in the CCPR1 registers which seems to be of 1 or 2 Tcy.
My questions:
a) The paragraph in bold, is it actualy including the rest of the interrupts as well? Found it quite unclear.
b) Is it any way to compensate the differences in time elapsed between succesive entries to the ISR?
Help appreciated.
I have implemented a clock, with the module CCP1 (compare mode) against TMR1 (counter mode).
To get a fixed duty cycle in RC2 pin, upon matching TMR1, the ISR loads alternatively two values in the CCPR1H:L registers.
Above ISR is high priority. Another one, running in low priority have no problems to coexist.
Regarding the latency, in the manual, I read:
For external interrupt events, such as the INT pins or the PORTB input change interrupt, the interrupt latency will be three to four instruction cycles.
The exact latency is the same for one or two-cycle instructions.
Having run all this through MPSIM I found a variation in the time elapsed between successives entries to the ISR, with the adequate allowance for the actual value loaded in the CCPR1 registers which seems to be of 1 or 2 Tcy.
My questions:
a) The paragraph in bold, is it actualy including the rest of the interrupts as well? Found it quite unclear.
b) Is it any way to compensate the differences in time elapsed between succesive entries to the ISR?
Help appreciated.
