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can I transfer data between two clock domain like that?

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tarkyss

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cdc_wp.pdf

can I transfer data between two clock domains like that?
I think it is dangerous, because the bits of the data may delay one cycle or two cycles, so some bit may be the current data, and some may be the previous data.but it is proved it can work (tap out), why?
ps,clk1 may be faster than clk2 or slower than clk2, in addition, there are some control signal not drawn here.
 

Hi,
This technique is safe for single bit signals
You can do this for data_bus only if it is gray coded, which ensures that only one bit changes at a time.
You are right in saying that this is dangerous for multi-bit signals.

For data_buses, another technique is used where the data_bus is validated by a single bit control signal which has been synchronized by using FFs (like the one in your diagram)

Check this paper which gives a very good explanation :

h**p://cadence.com/whitepapers/cdc_wp.pdf

The circuit I have mentioned above is in section 3.2

Any other pointers from anybody else will be useful.

B
 

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    tarkyss

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beowulf is right in saying tht

tarkyss , the image u referred to is simply the "Simplest SYNCHRONIZER".... it may or may not work depending on Metastability resolution time n clock frequencies ...but ofcourse itz for a single bit....
 

beowulf said:
Hi,
This technique is safe for single bit signals
You can do this for data_bus only if it is gray coded, which ensures that only one bit changes at a time.
You are right in saying that this is dangerous for multi-bit signals.

For data_buses, another technique is used where the data_bus is validated by a single bit control signal which has been synchronized by using FFs (like the one in your diagram)

Check this paper which gives a very good explanation :

h**p://cadence.com/whitepapers/cdc_wp.pdf

The circuit I have mentioned above is in section 3.2

Any other pointers from anybody else will be useful.

B
Click to expand...


Why isn't the single bit technique is not safe/applicable for data buses ?
 

I dont think this will work properly.J ust assume clk1 is 50 MHHz and clk2 is 100 MHZ then data will come at diffrent spped in clk1 and diffrent with clk2 and we will miss some bits.We wont be able to capture the data properly.
 

what I'm asking about is why this style works with single bit but not with data-bus ?
 

vikas_lakhanpal27 said:
I dont think this will work properly.J ust assume clk1 is 50 MHHz and clk2 is 100 MHZ then data will come at diffrent spped in clk1 and diffrent with clk2 and we will miss some bits.We wont be able to capture the data properly.
Click to expand...
In my understanding,it can work when 1/2<Fclk1/Fclk2<2;but in other conditions,use handshaking for better!
 

Omara,

what I'm asking about is why this style works with single bit but not with data-bus ?

I think it wont work with single bit also. The diagram u have attached is not correct.If u r transffering data between 2 clock domaind there shuld be some control signalson the basis of data will get latched.Moreover the clocks will be Phase too!
There shuld be some relation betwen clock else it will never happen.
Hope it will help u!
 

Hi all,

The question of Omara is judicious.

My opinion is that the double sync stage in case of clock domain transfer will work either with single bit or bus signals if special care is taken when designing the synchronizer from a synthesis point of view.

Otherwise, a FIFO can be used to ensure no corruption will happen in data transfers.

Have a nice day!
 

I think it can work properly, for it is a class asyn to syn structure.
 

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