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how to avoid the latch up problem?

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katrin

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linear data interpolator

I have a question regarding the latch up problem.
Why it is said that LATCH-UP can be triggered when voltages at the I/O pins that exceed the supply rails by more than a diode drop
 

it gives the standard design info...

about lathup use a pull down...
 

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    katrin

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tom_hanks said:
it gives the standard design info...

about lathup use a pull down...
Click to expand...

I am sorry to ask again, there are four pdf document on this link,

8-bit Linear Data Interpolator chip
Report on 8-bit Linear Data Interpolator chip
Asynchronous Serial Data Transmitter using VHDL and Verilog
Fully Custom CMOS 2:1 Multiplexor using SPICE

I have taken a quick look at these document, but I have not found much information about latch-up. could you please tell me which document do you refer to ? thanks
 

I believe you should connect the n-well to Vdd2 as it has a positive ripple. The n-well acts as the base of the parasitic pnp transistor and if a negative peak comes at the base -nwell- then it can switch on the pnp transistor and possibly sustain a latchup. But since the peaking in Vdd2 is positive, the pnp would still remain off, even with the ripple.

Generally you can avoid latch up by using guard rings. Basically you have to provide a number of n-taps on the n-well, all at Vdd2 potential itself.

Why don't u use Vdd2 supply for both the source and the substrate and avoid body effect?

These are my suggestions and I could be wrong :D
 

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    katrin

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hi
check out hte following link
it may help you



regards

analayout
 

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    katrin

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thanks for all the the help, I also think the connection of the bulk to Vdd2 with pisitive spike would be better
 

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