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layout techniques for high current

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drabos

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What is the main important things for the layout of an output stage which has to deliver high current (several amperes AC current) in CMOS technology?
 

if it is a high current circuit, transistors are large. split the transistor into several fingers and consider the width of the metals that deliver the current to the transistor. numbers of vias/contacts should also be taken into account so as not to suppress the desired current. ask the person in-charge about the current capacity of metals, vias, and contacts. if u fail to comply with this simple Dos, electromigration may be triggered.
 

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    drabos

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use large transistors with large DCGS/SCGS.
for long strip of poly, connect metal to both ends
put gardring around output transistors.
enough metal width, via number.
 

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    drabos

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hi stennor!

what you mean as DCGS/SCGS? could you explain me?
 

DCGS: drain contact to gate spacing
SCGS: source contact to gate spacing

larger spacing, more robust at high current high voltage
 

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    drabos

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only widening metal is not enough,
there is a max width, such as 30um, for a process, because of electronmigration(EM) effect.
you can place some slot in metal, to avoid EM effect.
if you have design rule about it, that's great!
 

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    drabos

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these maximum is not because of release stress in wide metal???
 

better tapping is also required. if you have high currents flowing in transistors, use lot of taps nearby, especially if it goes near the IO ring or a Pad.
regards,
 

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    drabos

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pvnk said:
better tapping is also required. if you have high currents flowing in transistors, use lot of taps nearby, especially if it goes near the IO ring or a Pad.
regards,
Click to expand...

what is tapping?
 

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