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What are Synthesis Pragmas and what's their effect?

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kunal1514

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Hi All,

Can any body tell me what are Synthesis Pragmas.

and How they effect.

Regard's

Kunal Mishra
 

Re: Synthesis Pragmas

Pragmas or synthesis directives are specially formatted comments. Thye should not contain any extra characters other than what is necessary for the synthesis directive.
There are several types of pragmas supported by various RTL synthesis tool: Synthesis On and Off Directives ( Does code selection for the synthesis tool ), Architecture selection directive (For example adder can be inferred as ripple or carry lookahead ) , Case statement directive ( Full case, parallel case ), Module Template directive , Function and Task Mapping Directives , Set and Reset Synthesis Directives etc.
 
Synthesis Pragmas

yes and they are given as a comment in your verilog code to the synthesis tool
 

Synthesis Pragmas

Hi,
pragma is used to skip unsynthesizable lines in the design. For simulation and debugging u may add some lines into design. so design complier skips the portion between pragma off and on.
 

Re: Synthesis Pragmas

pragma is used to skip unsynthesizable lines in the design
Click to expand...

That's only part of it. Like the other posters said, pragmas are "compiler directives." You can use a pragma to turn parsing on/off (//synopsys translate off), that's a common use. But pragmas can also tell the synthesis-tool to choose an algorithm/strategy, like choosing a FCLA adder (instead of CSEL or RPL), or choosing a multiplier architecture, etc.

Simulation tools generally ignore the directives, and that's a problem...because certain pragmas (//synopsys full_case parallel_case) change the behavior of the synthesized-output (compare to the soruce Verilog.)

Systemverilog has a few new language-keywords to help with designer-intent on case/if/else synthesis: priority, unique.
 

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