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EDA_hg81

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What I am doing is to use Spartan-3 to transfer the incoming image data to the display.

But the same idea gets two different results with two different codes:

Code 1:
FDDRRSE_OUT12 : FDDRRSE
-- generic map (INIT => '0')
port map (
Q => B_RSDS_OUT(3),
C0 => CLK_IN,
C1 => DDR_CLK,
CE => ENB,
D0 => B_RE(6),
D1 => B_RE(7),
R => GND,
S => GND
);
process ( CLK_IN )

begin
if ( CLK_IN'EVENT and CLK_IN = '1' )then
R_RE <= R_IN;
G_RE <= G_IN;
B_RE <= B_IN;
end if;
end process;

with those above code the image lost info along edge profile.

Code 2:

FDDRRSE_OUT12 : FDDRRSE
-- generic map (INIT => '0')
port map (
Q => B_RSDS_OUT(3),
C0 => CLK_IN,
C1 => DDR_CLK,
CE => ENB,
D0 => B_RE(6),
D1 => B_RE(7),
R => GND,
S => GND
);

process ( R_IN, G_IN,B_IN )
begin

R_RE <= R_IN;
G_RE <= G_IN;
B_RE <= B_IN;

end process;

with those above code the image looks very good.

What is the possible reason for this?
 

In your first code you are assigning the colors on the active edges of your clock. In your second code you are checking any event on input colors. second approach looks good. but I suggest you to write the three color assignment statement outside the process statement concurrently. Try this it will work fine.

Good Luck!!
 

    E

    EDA_hg81

    Points: 2
    Helpful Answer Positive Rating
Hi

From your code , its clearly visible that you are actually tieing the intermediate results of each colour to next block(or may be output). hence it becomes logical to put those signal whose transition cause a change in output in sensitivity list . thus it is better u add all the three signal (R,G &B) in the sensitivity list

nav_vlsi
 

    E

    EDA_hg81

    Points: 2
    Helpful Answer Positive Rating
make sure you are using the same clock for videogenrator(HSYNC, VSYNC, DE) and control data.


Also your code didn't show what are you driving during blank interval ie DE = '0'


regards,
 

    E

    EDA_hg81

    Points: 2
    Helpful Answer Positive Rating
Thank you all very much.

Let me try and I will let you know the result.

Added after 19 minutes:

nav_vlsi said:
Hi

From your code , its clearly visible that you are actually tieing the intermediate results of each colour to next block(or may be output). hence it becomes logical to put those signal whose transition cause a change in output in sensitivity list . thus it is better u add all the three signal (R,G &B) in the sensitivity list

nav_vlsi
Click to expand...

I tried this way. But it didn't work well.

Added after 2 minutes:

Iouri said:
make sure you are using the same clock for videogenrator(HSYNC, VSYNC, DE) and control data.


Also your code didn't show what are you driving during blank interval ie DE = '0'


regards,
Click to expand...

I didn't use DE signal.

Should I assign all "00000000" to each color during blank interval?

Added after 26 minutes:

I have to process each color before outputting them.

Each processing block has to be synchronized with pixel clock.

I have tried if any block is involved with clock, the result is going to be shitty.

What i should do?

Thank you in advance.

Added after 24 minutes:

I have changed the code as followings, it is working well.

process ( CLK_IN, DE )
begin
if ( DE = '1' )then
R_GE <= R_IN;
G_GE <= G_IN;
B_GE <= B_IN;
else
R_GE <= "00000000";
G_GE <= "00000000";
B_GE <= "00000000";

end if;
end process;
 

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