PLL settling time question

Settling time can be simply defined as the time that PLL needs to lock after a jump or change in its inputs (may be not very accurate).

Anyway, a strange phenomena occures in PLL, I saw in second and third order PLL, that's , in case of small frequency step, there's almost no slipping in the close loop dynamic responce, wherease in realively large step, there's sometimes one cycle-slipping.
As in the attached figure,
- the blue VCO control line output from loop filter, corresponds to Δf=2MHz step in the PLL input,
- and the red the Vc signal, corresponds to Δf=10MHz step in the PLL input.


Can someone discuss some reasons for that as well as methods to compansate?

Thanks and Regards,
Ahmad,

When the frequency step is large, the control voltage cannot reach the final value in one cycle, so it keeps rising until the value is reached, then the voltage keeps up and down near the locked voltage. When the step is small, the voltage can reach the final value in one cycle. That's the difference.

That means it's not totally predictable?, i.e. number of slipped-cycles?
Can it skipp more than one cycle?
How to compansate?

I think you can calculate how fast the control voltage can change. For a charpge pump time PLL, t is determined by the charge pump current and the capacitor in the loop filter.

For your 2MHz case, it takes about 0.2msec (from 0.2 to 0.4) to reach 100mV, and 500mV is reached at about 1msec (from 0.2 to 1.2) for the 10MHz case. The time is roughly propotional to the frequency step since the slope is the same. It happens to spend one more cycle because your cycle period is 0.6msec. If the frequency step is 12MHz, the control voltage will reach the target 600mV at 1.5msec. I think it is not related to the cycle period.

If you want to shorten the time, I think you have to enlarge the detection gain (phase/frequency error to control voltage, or to VCO frequency). But do care the stability.