Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Synthesizing VHDL code of a PLL

Status
Not open for further replies.
ahmad_abdulghany

ahmad_abdulghany

Advanced Member level 4
Joined
Apr 12, 2005
Messages
1,206
Helped
102
Reputation
206
Reaction score
22
Trophy points
1,318
Location
San Jose, California, USA
Activity points
11,769
Hi,
Simple question,
Can a complete PLL (digital) be synthesized from a VHDL or Vrilog code?
I mean the structural level not only behavioural one!
Is that case practical?
Thanks in advance,
Ahmad,
 

pll vhdl

ahmad_abdulghany said:
Hi,
Simple question,
Can a complete PLL (digital) be synthesized from a VHDL or Vrilog code?
I mean the structural level not only behavioural one!
Is that case practical?
Thanks in advance,
Ahmad,
Click to expand...

Salam 3alikom,

Actually PLLs has Analog circuits which mean that the sunthesizrs could not treat i as digital hardware completly.
Generally, PLLs are included in the ASIC library vendors. It supplies SIMULATION models.

In FPGA worlds:
You may use the PLLs of the vendor, XILINX or ALTERA...
They also supplies BLACK BOX models which immulate PLLs.
That BB are modelated in VHDL or VERILOG so you can modefied its parameters, then the simulator or the synthesizer will take care very well for these parameters.

Configuration of the PLL's paramaters should be modified at the power-up of the IC. You will not be able to change in real-time.

خليل عبد الرحيم
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top