davyzhu
Advanced Member level 1
Hi,
I want to write SystemVerilog testbench for traditional Verilog module.
But I have no idea how to SystemVerilog interface to traditional Verilog module? Can I both use modport and instance the module? Or is there any walk around method? Thanks!
and
Best regards,
Davy
I want to write SystemVerilog testbench for traditional Verilog module.
But I have no idea how to SystemVerilog interface to traditional Verilog module? Can I both use modport and instance the module? Or is there any walk around method? Thanks!
Code:
//----- Verilog Module-----
module dut(
CLK,
RESET,
DATA,
... ...
);
input CLK, RESET;
output DATA;
...
//-----------------------------------
Code:
//----- SystemVerilog Interface-----
interface dut_tb_if;
bit clk,reset,data;
modport... ...
//---------------------------------------------Davy
