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Re: what are the challenges when porting 0.18 um design to 0
I ever referenced a design with 0.18um CMOS, then I needed to port it to the 0.13um CMOS and 90nm CMOS. In my memories, we did not not concern much about the scaled down process. We just obey the design strategy and design rules. Then it works OK.
The only concern I rember is that, in low power design, the scaled down process brings more HCE(hot carrier effect) and leakage current is more seriously.
yes, you have to redesign because of the process is different. For digital dsign, the scaled down process has minimum impact to the design , the RTL code for synthesis may not be changed or changed a it.But for analog, you must iterate the design procedures.
In redesign your blocks with scaled down process, you can try to scaled down the size of the original part according the new process. Because you circuit performance is detremind by the W/L, so it is meaningful to scaled down your size. Then you need to optimize it based on it. You need not change the topology lot.
Re: what are the challenges when porting 0.18 um design to 0
in analog design (mostly are 3.3v or 2.5V) , the whole circuit will not differ too much, because the device u used are almost the same. so the porting can be directly, except the layout should be changed to fit the design rule of 0.13um process.
Usually, contact & via should be shrink to fit the design rule.
Is there any tool can to this job automatically ?
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